IS24C02
IS24C02
2,048-BIT SERIAL ELECTRICALLY
ERASABLE PROM
ISSI
AUGUST 1998
ISSI
®
®
FEATURES
• Low power CMOS
— Active current less than 2 mA
— Standby current less than 8
µA
• Hardware write protection
— Write control pin
• Internally organized as 256 x 8
• Two-wire serial interface
— Bidirectional data transfer protocol
• 8-Byte page-write mode
— Minimized total write time per byte
• Automatic word address incrementing
— Sequential register read
• Self-timed write cycle
— Maximum write cycle time of 10 ms
• 400 KHz Compatibility
• Endurance: 1, 000,000 cycles per byte
• 8-pin PDIP, TSSOP, MSOP or SOIC packages
• Filtered inputs for noise suppression
OVERVIEW
The IS24C02 is a low cost 2,048-bit serial EEPROM. It is
fabricated using
ISSI
’s advanced CMOS EEPROM tech-
nology and operates from a single supply.
The IS24C02 is internally organized as a 256 x 8 memory
bank. The IS24C02 features a serial interface and soft-
ware protocol allowing operation on a simple 2-wire bus.
Up to eight IS24C02s may be connected to the
2-wire bus by programming the A0, A1, and A2 inputs.
FUNCTIONAL BLOCK DIAGRAM
Vcc
8
HIGH VOLTAGE
GENERATOR,
TIMING AND
CONTROL
SDA
5
X
DECODER
SCL
6
WC
7
SLAVE ADDRESS
REGISTER &
COMPARATOR
Load
CONTROL
LOGIC
64
32 x 64
MEMORY
CORE
Inc.
A2
3
A1
2
A0
1
WORD ADDRESS
COUNTER
32
Y
DECODER
GND
4
nMOS
ACK
Clock
DI/O
DATA
REGISTER
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which
may appear in this publication. © Copyright 1998, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc.
EE009-1F
08/20/98
1
IS24C02
PIN CONFIGURATION
8-Pin DIP, TSSOP, MSOP and SOIC
ISSI
PIN DESCRIPTIONS
A0-A2
Address Inputs
Serial Data I/O
Serial Clock Input
Write Control Input
Power
Ground
SDA
SCL
®
A0
A1
A2
GND
1
2
3
4
8
7
6
5
VCC
WC
SCL
SDA
WC
Vcc
GND
PIN DESCRIPTIONS
Serial Clock (SCL)
- The SCL input is used to clock all data
into and out of the device. In the WRITE mode, data must
remain stable when SCL is HIGH. In the READ mode, data
is clocked out on the falling edge of SCL.
Serial Data (SDA)
- The SDA pin is a bidirectional pin used
to transfer data into and out of the device. Data may
change only when SCL is LOW. It is an open-drain output,
and may be wire-ORed with any number of open-drain or
open-collector outputs.
A0, A1, and A2
- The address inputs are used to set the
least significant three bits of the slave address. These
inputs may be tied HIGH or LOW, or they may be actively
driven. These inputs allow up to eight IS24C02 devices to
be connected together on the bus. When left floating, A0,
A1 and A2 are pulled to ground. The default values are
zeros.
Write Control (
WC
)
- The Write Control input is used to
disable any attempt to write to the memory. When HIGH,
the memory is protected; when LOW, the write function is
normal. The part can be read independent of the state of
WC
pin. When not connected this pin will be pulled LOW.
GENERAL DESCRIPTION
The IS24C02 features a SERIAL communication, and
supports bidirectional data transmission protocol allowing
operation on a simple two-wire bus between the different
devices connected somewhere on the system bus. The
two-wire bus is defined as a serial data line (SDA), and a
serial clock line (SCL). (Refer to Figure 1. Typical System
Bus Configuration.)
The protocol defines any device that sends data onto the
SDA bus as a transmitter, and the receiving device as a
receiver. The device controlling the data transmission is
named MASTER device, and the controlled device is
named SLAVE device. In all cases, the IS24C02 will be a
slave device, since it never initiates any data transfers. Up
to eight IS24C02 can be connected to the bus. Device's
physical address inputs A0-A2 must be connected to
either Vcc or GND. When left floating, A0, A1 and A2 are
pulled to ground. The default values are zeros.
Following a START condition, the MASTER (transmitter)
device must initiate the “Device Addressing Byte” includ-
ing device type identifier, device address, and a read or
write operation to select a slave device (receiver) con-
nected to the system bus. The receiver will then respond
with an ACKnowledge by pulling the SDA line LOW.
The ACKnowledge is used to indicate successful data
transfers. The transmitting device will release the data bus
(SDA goes HIGH) after transmitting eight bits (one data bit
is transfered at the falling edge of each clock cycle). During
the ninth clock cycle, the receiver will pull the SDA line
LOW to ACKnowledge the transmitter that it received the
eight bits of data. (Refer to Figure 2. ACKnowledge Re-
sponse from Receiver Diagram.)
ENDURANCE AND DATA RETENTION
The IS24C02 is designed for applications requiring high-
endurance write cycles and unlimited read cycles. It pro-
vides 10 years of secure data retention, with or without
power applied, after the execution of 1,000,000 write
cycles.
APPLICATIONS
The IS24C02 is ideal for high volume applications requir-
ing low power and low density storage. This device uses
a low-cost, space-saving 8-pin plastic package. Candi-
date applications include robotics, alarm devices, elec-
tronic locks, meters and instrumentation.
2
Integrated Silicon Solution, Inc.
EE009-1F
08/20/98
IS24C02
DEVICE OPERATION
START and STOP Conditions
Both SDA and SCL lines remain HIGH when the SDA bus
is not busy. A HIGH-to-LOW transition of SDA line, while
SCL is HIGH, is defined as the START condition. A LOW-
to-High transition of SDA line, while SCL is HIGH, is
defined as the STOP condition. (Refer to Figure 3. Start
and Stop Conditions.)
Data Validity Protocol
One data bit is transferred during each clock cycle. The
data on the SDA line must remain stable during the HIGH
period of the clock cycle, because changes on SDA line
during the SCL HIGH period will be interpreted as START
or STOP control signals. (Refer to Figure 4. Data Validity
Protocol.)
Device Addressing Byte Definitions
The most significant four bits of Device Addressing Byte
(Bit 7 to Bit 4) are defined as the device type identifier. For
IS24C02, this is fixed as 1010. The next three significant
address bits (Bit 3 to Bit 1) address a particular device. Up
to eight IS24C02 devices can be connected on the bus.
These eight addresses are defined by the state of the A0,
A1, and A2 inputs. The last bit Bit 0 defines the write or read
operation to be performed. When set to “1”, a READ
operation is selected; when set to “0” a WRITE operation
is selected. (Refer to Figure 5. Device Addressing Byte
Definitions.)
ISSI
®
Page Write
The IS24C02 is capable of 8-byte page- WRITE operation.
A page-WRITE is initiated in the same manner as a byte
write, but instead of terminating the internal write cycle
after the first data word is transfered, the master device
can transmit up to 7 more words. After the receipt of each
data word, the IS24C02 responds immediately with an
ACKnowledge on SDA line, and the four lower order data
word address bits are internally incremented by one while
the four higher order bits of the data word address remain
constant. If the master device should transmit more than
8 words, prior to issuing the STOP condition, the address
counter will “roll over,” and the previously written data will
be overwritten. All inputs are disabled until completion of
the internal WRITE cycle. (Refer to Figure 6. Write Opera-
tion for the Address, ACKnowledge, and Data Transfer
Sequence.)
Acknowledge Polling
Once the internal write cycle has started and the
IS24C02 inputs are disabled, acknowledge polling can be
initiated. This involves sending a start condition followed
by the Device Addressing Byte. The read/write bit is
representive of the operation desired. Only if the internal
write cycle has been completed will the IS24C02 respond
with an acknowledge on the SDA bus allowing the read or
write sequence to continue.
READ OPERATION
READ operations are initiated in the same manner as
WRITE operations, except that the read/write bit of the
device addressing byte is set to “1”. There are three READ
operation options: current address read, random address
read and sequential read.
Current Address Read
The IS24C02 contains an internal address counter which
maintains the address of the last data word accessed,
incremented by one. For example, if the previous opera-
tion either a read or write operation addressed to the
address location n, the internal address counter would
increment to address location n+1. When the IS24C02
receives the Device Addressing Byte with a READ opera-
tion (read/write bit set to “1”), it will respond an ACKnowledge
and transmit the 8-bit data word stored at address location
n+1. If the Current Address READ operation only ac-
cesses a single byte of data, the master device terminates
the Current Address READ operation by pulling
ACKnowledge HIGH (lack of ACKnowledge) indicating the
last data word to be read, followed by a STOP condition.
(Refer to Figure 7. Current Address Read Diagram.)
WRITE OPERATION
Byte Write
For a WRITE operation, the IS24C02 requires another
8-bit data word address following the Device Addressing
Byte and ACKnowledgement. This data word address
provides access to any one of the 256 data words of
device's memory array.
Upon receipt of the data word address, the IS24C02
responds with an ACKnowledge on SDA, and waits for the
next 8-bit data word, then again responding with an
ACKnowledge. The master device terminates the Byte
Write Operation by generating a STOP condition, after-
ward the IS24C02 begins the internal WRITE cycle to the
nonvolatile memory array. Refer to Write Cycle Timing. All
inputs are disabled during this write cycle and the device
will not respond to any requests from the master. (Refer to
Figure 6. Write Operation for the Address, ACKnowledge,
and Data Transfer Sequence.)
Integrated Silicon Solution, Inc.
EE009-1F
08/20/98
3
IS24C02
Random Access Read
Random Address READ operation allows the master
device to access any memory location in a random fash-
ion. This operation involves a two-step process. First, the
master device generates a START condition and initiates
Device Addressing Byte with a dummy WRITE operation
(read/write bit sets to “0”), followed by the address of the
data word the master device is to READ. This procedure
stores the desired address of data word to the internal
address counter of the IS24C02.
After the data word address ACKnowledge is received by
the master device, the master device now initiates a
CURRENT ADDRESS READ
by sending Device Ad-
dressing Byte with a READ operation (read/write bit sets to
“1”). The IS24C02 responds with an ACKnowledge and
transmits the eight data bits stored at the address location
where the master device is to READ. At this point, the
master device terminates the operation by pulling
ACKnowledge HIGH (lack of ACKnowledge) indicating the
last data word to be read, followed by a STOP condition.
(Refer to Figure 8. Random Address Read Diagram.)
ISSI
®
Sequential Read
Sequential Reads can be initiated as either a Current
Address Read or Random Address Read. The first data
word is transmitted as with the other byte read modes, the
master device now responds with an ACKnowledge indi-
cating that it requires additional data from the IS24C02.
The IS24C02 continues to output data for each
ACKnowledge received. the master device terminates the
sequential READ operation by pulling ACKnowledge HIGH
(lack of ACKnowledge) indicating the last data word to be
read, followed by a STOP condition.
The data output is sequential, with the data from
address n followed by the date from address n+1, ... etc.
The address counter increments by one automatically,
allowing the entire memory contents to be serially read
during sequential read operation. When the memory ad-
dress boundry (address 255) is reached, the address
counter “rolls over” to address 0, and the IS24C02 contin-
ues to output data for each ACKnowledge received. (Refer
to Figure 9. Sequential Read Operation Starting with a
Random Address READ Diagram.)
Vcc
SDA
SCL
Master
Transmitter/
Receiver
Slave
Receiver
Slave
Transmitter/
Receiver
Master
Transmitter
Master
Transmitter/
Receiver
Figure 1. Typical System Bus Configuration
SCL from
Master
1
8
9
Data Output
from
Transmitter
t
AA
t
AA
Data Output
from
Receiver
ACK
Figure 2. ACKnowledge Response from Receiver
4
Integrated Silicon Solution, Inc.
EE009-1F
08/20/98
IS24C02
ISSI
®
STOP
Condition
SDA
START
Condition
SCL
Figure 3. START and STOP Conditions
SCL
SDA
Data Stable
Data Stable
Figure 4. Data Validity Protocol
BIT 7
BIT 4 BIT 3
BIT 1 BIT 0
1
0
1
0
A
2
A
1
A
0
R
W
BIT 7 - BIT 4:
BIT 3 - BIT 1:
BIT 0:
Are defined as the Device Type Identifier.
For IS24C02, this is fixed as 1010.
Address a particular device.
Defines the Write or Read Operation to be performed.
1: Read Operation
0: Write Operation
Figure 5. Device Addressing Byte Definitions
Integrated Silicon Solution, Inc.
EE009-1F
08/20/98
5
