without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
04/28/05
1
IS41C16256A
IS41LV16256A
FUNCTIONAL BLOCK DIAGRAM
OE
WE
LCAS
UCAS
CAS
CLOCK
GENERATOR
WE
CONTROL
LOGICS
OE
CONTROL
LOGIC
ISSI
®
CAS
WE
OE
RAS
RAS
CLOCK
GENERATOR
DATA I/O BUS
REFRESH
COUNTER
DATA I/O BUFFERS
ROW DECODER
RAS
COLUMN DECODERS
SENSE AMPLIFIERS
I/O0-I/O15
MEMORY ARRAY
262,144 x 16
ADDRESS
BUFFERS
A0-A8
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
04/28/05
IS41C16256A
IS41LV16256A
TRUTH TABLE
Function
Standby
Read: Word
Read: Lower Byte
Read: Upper Byte
Write: Word (Early Write)
Write: Lower Byte (Early Write)
Write: Upper Byte (Early Write)
Read-Write
(1,2)
EDO Page-Mode Read
(2)
1st Cycle:
2nd Cycle:
Any Cycle:
EDO Page-Mode Write
(1)
1st Cycle:
2nd Cycle:
EDO Page-Mode
Read-Write
(1,2)
Hidden Refresh
2)
RAS-Only
Refresh
CBR Refresh
(3)
1st Cycle:
2nd Cycle:
RAS
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
LCAS UCAS
H
L
L
H
L
L
H
L
H→L
H→L
L→H
H→L
H→L
H→L
H→L
L
L
H
L
H
L
H
L
L
H
L
L
H→L
H→L
L→H
H→L
H→L
H→L
H→L
L
L
H
L
WE
X
H
H
H
L
L
L
H→L
H
H
H
L
L
H→L
H→L
H
L
X
X
OE
X
L
L
L
X
X
X
L→H
L
L
L
X
X
L→H
L→H
L
X
X
X
Address t
R
/t
C
X
ROW/COL
ROW/COL
ROW/COL
ROW/COL
ROW/COL
ROW/COL
ROW/COL
ROW/COL
NA/COL
NA/NA
ROW/COL
NA/COL
ROW/COL
NA/COL
ROW/COL
ROW/COL
ROW/NA
X
I/O
ISSI
High-Z
D
OUT
Lower Byte, D
OUT
Upper Byte, High-Z
Lower Byte, High-Z
Upper Byte, D
OUT
D
IN
Lower Byte, D
IN
Upper Byte, High-Z
Lower Byte, High-Z
Upper Byte, D
IN
D
OUT
, D
IN
D
OUT
D
OUT
D
OUT
D
IN
D
IN
D
OUT
, D
IN
D
OUT
, D
IN
D
OUT
D
OUT
High-Z
High-Z
®
Read L→H→L
Write L→H→L
L
H→L
Notes:
1. These WRITE cycles may also be BYTE WRITE cycles (either
LCAS
or
UCAS
active).
2. These READ cycles may also be BYTE READ cycles (either
LCAS
or
UCAS
active).
3. At least one of the two
CAS
signals must be active (LCAS or
UCAS).
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
04/28/05
3
IS41C16256A
IS41LV16256A
Functional Description
The IS41C16256A and IS41LV16256A is a CMOS DRAM
optimized for high-speed bandwidth, low power applica-
tions. During READ or WRITE cycles, each bit is uniquely
addressed through the 18 address bits. These are en-
tered nine bits (A0-A8) at a time. The row address is
latched by the Row Address Strobe (RAS). The column
address is latched by the Column Address Strobe (CAS).
RAS
is used to latch the first nine bits and
CAS
is used the
latter nine bits.
The IS41C16256A and IS41LV16256A has two
CAS
con-
trols,
LCAS
and
UCAS.
The
LCAS
and
UCAS
inputs
internally generates a
CAS
signal functioning in an iden-
tical manner to the single
CAS
input on the other 256K x
16 DRAMs. The key difference is that each
CAS
controls
its corresponding I/O tristate logic (in conjunction with
OE
and
WE
and
RAS). LCAS
controls I/O0 through I/O7 and
UCAS
controls I/O8 through I/O15.
The IS41C16256A and IS41LV16256A
CAS
function is
determined by the first
CAS
(LCAS or
UCAS)
transitioning
LOW and the last transitioning back HIGH. The two
CAS
controls give the IS41C16256A both BYTE READ and
BYTE WRITE cycle capabilities.
ISSI
Refresh Cycle
®
To retain data, 512 refresh cycles are required in each
8 ms period. There are two ways to refresh the memory.
1. By clocking each of the 512 row addresses (A0 through
A8) with
RAS
at least once every 8 ms. Any read, write,
read-modify-write or
RAS-only
cycle refreshes the ad-
dressed row.
2. Using a
CAS-before-RAS
refresh cycle.
CAS-before-
RAS
refresh is activated by the falling edge of
RAS,
while holding
CAS
LOW. In
CAS-before-RAS
refresh
cycle, an internal 9-bit counter provides the row ad-
dresses and the external address inputs are ignored.
CAS-before-RAS
is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Extended Data Out Page Mode
EDO page mode operation permits all 512 columns within
a selected row to be randomly accessed at a high data
rate.
In EDO page mode read cycle, the data-out is held to the
next
CAS
cycle’s falling edge, instead of the rising edge.
For this reason, the valid data output time in EDO page
mode is extended compared with the fast page mode. In
the fast page mode, the valid data output time becomes
shorter as the
CAS
cycle time becomes shorter. There-
fore, in EDO page mode, the timing margin in read cycle
is larger than that of the fast page mode even if the
CAS
cycle time becomes shorter.
In EDO page mode, due to the extended data function, the
CAS
cycle time can be shorter than in the fast page mode
if the timing margin is the same.
The EDO page mode allows both read and write opera-
tions during one
RAS
cycle, but the performance is
equivalent to that of the fast page mode in that case.
Memory Cycle
A memory cycle is initiated by bring
RAS
LOW and it is
terminated by returning both
RAS
and
CAS
HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum t
RAS
time has expired. A new
cycle must not be initiated until the minimum precharge
time t
RP
, t
CP
has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of
CAS
or
OE,
whichever occurs last, while holding
WE
HIGH. The
column address must be held for a minimum time speci-
fied by t
AR
. Data Out becomes valid only when t
RAC
, t
AA
,
t
CAC
and t
OEA
are all satisfied. As a result, the access time
is dependent on the timing relationships between these
parameters.
Power-On
After application of the V
CC
supply, an initial pause of
200 µs is required followed by a minimum of eight initial-
ization cycles (any combination of cycles containing a
RAS
signal).
During power-on, it is recommended that
RAS
track with
V
CC
or be held at a valid V
IH
to avoid current surges.
Write Cycle
A write cycle is initiated by the falling edge of
CAS
and
WE,
whichever occurs last. The input data must be valid
at or before the falling edge of
CAS
or
WE,
whichever
occurs last.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
04/28/05
IS41C16256A
IS41LV16256A
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
T
V
CC
I
OUT
P
D
T
A
T
STG
Parameters
Voltage on Any Pin Relative to GND
Supply Voltage
Output Current
Power Dissipation
Commercial Operation Temperature
Storage Temperature
5V
3.3V
5V
3.3V
Rating
–1.0 to +7.0
-0.5 to 4.6
–1.0 to +7.0
-0.5 to 4.6
50
1
0 to +70
–55 to +125
Unit
V
V
V
V
mA
W
°C
°C
ISSI
®
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltages are referenced to GND.)
Symbol
V
CC
V
IH
V
IL
T
A
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Commercial Ambient Temperature
5V
3.3V
5V
3.3V
5V
3.3V
Min.
4.5
3.0
2.4
2.0
–1.0
–0.3
0
Typ.
5.0
3.3
—
—
—
—
—
Max.
5.5
3.6
V
CC
+ 1.0
V
CC
+ 0.3
0.8
0.8
+70
Unit
V
V
V
°C
CAPACITANCE
(1,2)
Symbol
C
IN
1
C
IN
2
C
IO
Parameter
Input Capacitance: A0-A8
Input Capacitance:
RAS, UCAS, LCAS, WE, OE
Data Input/Output Capacitance: I/O0-I/O15
Max.
5
7
7
Unit
pF
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25°C, f = 1 MHz,
Integrated Silicon Solution, Inc. — 1-800-379-4774
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