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IS42S16400J-5BL

Synchronous DRAM, 4MX16, 5ns, CMOS, PBGA54, 8 X 8 MM, 0.80 MM PITCH, ROHS COMPLIANT, TFBGA-54

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厂商名称:Integrated Silicon Solution ( ISSI )

器件标准:

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器件参数
参数名称
属性值
是否Rohs认证
符合
厂商名称
Integrated Silicon Solution ( ISSI )
零件包装代码
BGA
包装说明
TFBGA, BGA54,9X9,32
针数
54
Reach Compliance Code
compliant
ECCN代码
EAR99
Factory Lead Time
6 weeks
访问模式
FOUR BANK PAGE BURST
最长访问时间
4.8 ns
其他特性
AUTO/SELF REFRESH
最大时钟频率 (fCLK)
200 MHz
I/O 类型
COMMON
交错的突发长度
1,2,4,8
JESD-30 代码
S-PBGA-B54
长度
8 mm
内存密度
67108864 bit
内存集成电路类型
SYNCHRONOUS DRAM
内存宽度
16
功能数量
1
端口数量
1
端子数量
54
字数
4194304 words
字数代码
4000000
工作模式
SYNCHRONOUS
最高工作温度
70 °C
最低工作温度
组织
4MX16
输出特性
3-STATE
封装主体材料
PLASTIC/EPOXY
封装代码
TFBGA
封装等效代码
BGA54,9X9,32
封装形状
SQUARE
封装形式
GRID ARRAY, THIN PROFILE, FINE PITCH
认证状态
Not Qualified
刷新周期
4096
反向引出线
NO
座面最大高度
1.2 mm
自我刷新
YES
连续突发长度
1,2,4,8,FP
最大压摆率
0.09 mA
最大供电电压 (Vsup)
3.6 V
最小供电电压 (Vsup)
3 V
标称供电电压 (Vsup)
3.3 V
表面贴装
YES
技术
CMOS
温度等级
COMMERCIAL
端子形式
BALL
端子节距
0.8 mm
端子位置
BOTTOM
宽度
8 mm
文档预览
IS42S16400J
IS45S16400J
1 Meg Bits x 16 Bits x 4 Banks (64-MBIT)
SYNCHRONOUS DYNAMIC RAM
FEATURES
Clock frequency: 200, 166, 143, 133 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Internal bank for hiding row access/precharge
• Single 3.3V power supply
• LVTTL interface
• Programmable burst length
– (1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• Self refresh modes
• Auto refresh (CBR)
• 4096 refresh cycles every 64 ms (Com, Ind, A1
grade) or 16ms (A2 grade)
• Random column address every clock cycle
• Programmable CAS
latency (2, 3 clocks)
• Burst read/write and burst read/single write
operations capability
• Burst termination by burst stop and precharge
command
OPTIONS
• Package:
54-pin TSOP II
54-ball TF-BGA (8mm x 8mm)
60-ball TF-BGA (10.1mm x 6.4mm)
• Operating Temperature Range
Commercial (0
o
C to +70
o
C)
Industrial (-40
o
C to +85
o
C)
Automotive Grade A1 (-40
o
C to +85
o
C)
Automotive Grade A2 (-40
o
C to +105
o
C)
JANUARY 2014
OVERVIEW
ISSI
's 64Mb Synchronous DRAM is organized as 1,048,576
bits x 16-bit x 4-bank for improved performance. The
synchronous DRAMs achieve high-speed data transfer
using pipeline architecture. All inputs and outputs signals
refer to the rising edge of the clock input.
KEY TIMING PARAMETERS
Parameter
Clk Cycle Time
CAS Latency = 3
CAS Latency = 2
Clk Frequency
CAS Latency = 3
CAS Latency = 2
Access Time from Clock
CAS Latency = 3
CAS Latency = 2
-5
5
7.5
200
133
4.8
5.4
-6
6
7.5
166
133
5.4
5.4
-7
7
7.5
143
133
5.4
5.4
Unit
ns
ns
Mhz
Mhz
ns
ns
ADDRESS TABLE
Parameter
Configuration
Refresh Count
4M x 16
1M x 16 x 4
banks
Com./Ind.
4K/64ms
A1
4K/64ms
A2
4K/16ms
A0-A11
A0-A7
BA0, BA1
A10/AP
Row Addresses
Column Addresses
Bank Address Pins
Auto Precharge Pins
Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be ex-
pected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon
Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
12/17/2013
1
IS42S16400J
IS45S16400J
GENERAL DESCRIPTION
The 64Mb SDRAM is a high speed CMOS, dynamic
random-access memory designed to operate in 3.3V
memory systems containing 67,108,864 bits. Internally
configured as a quad-bank DRAM with a synchronous
interface. Each 16,777,216-bit bank is organized as 4,096
rows by 256 columns by 16 bits.
The 64Mb SDRAM includes an AUTO REFRESH MODE,
and a power-saving, power-down mode. All signals are
registered on the positive edge of the clock signal, CLK.
All inputs and outputs are LVTTL compatible.
The 64Mb SDRAM has the ability to synchronously burst
data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks
to hide precharge time and the capability to randomly
change column addresses on each clock cycle during
burst access.
A self-timed row precharge initiated at the end of the burst
sequence is available with the AUTO PRECHARGE function
enabled. Precharge one bank while accessing one of the
other three banks will hide the precharge cycles and provide
seamless, high-speed, random-access operation.
SDRAM
read and write accesses are burst oriented starting
at a selected location and continuing for a programmed
number of locations in a programmed sequence. The
registration of an ACTIVE command begins accesses,
followed by a READ or WRITE command. The ACTIVE
command in conjunction with address bits registered are
used to select the bank and row to be accessed (BA0,
BA1 select the bank; A0-A11 select the row). The READ
or WRITE commands in conjunction with address bits
registered are used to select the starting column location
for the burst access.
Programmable READ or WRITE burst lengths consist of
1, 2, 4 and 8 locations, or full page, with a burst terminate
option.
FUNCTIONAL BLOCK DIAGRAM
CLK
CKE
CS
RAS
CAS
WE
A10
DQM
COMMAND
DECODER
&
CLOCK
GENERATOR
DATA IN
BUFFER
16
16
MODE
REGISTER
12
REFRESH
CONTROLLER
DQ 0-15
SELF
REFRESH
CONTROLLER
A11
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA0
BA1
12
16
DATA OUT
BUFFER
V
DD
/V
DDQ
GND/GNDQ
16
REFRESH
COUNTER
4096
4096
4096
4096
ROW DECODER
MULTIPLEXER
12
MEMORY CELL
ARRAY
ROW
ADDRESS
LATCH
12
ROW
ADDRESS
BUFFER
BANK 0
SENSE AMP I/O GATE
COLUMN
ADDRESS LATCH
8
256K
(x 16)
BANK CONTROL LOGIC
BURST COUNTER
COLUMN
ADDRESS BUFFER
COLUMN DECODER
8
2
Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
12/17/2013
IS42S16400J
IS45S16400J
PIN CONFIGURATION
PACKAge Code: B 54 BALL Tf-BgA (Top View) (8 mm x 8 mm Body, 0.8 mm Ball Pitch)
1 2 3 4 5 6 7 8 9
A
B
C
D
E
F
G
H
J
GND DQ15 GNDQ
DQ14 DQ13 VDDQ
DQ12 DQ11 GNDQ
DQ10 DQ9 VDDQ
DQ8
NC
GND
CKE
A9
A6
A4
VDDQ DQ0
GNDQ DQ2
VDDQ DQ4
GNDQ DQ6
VDD
DQ1
DQ3
DQ5
VDD DQML DQ7
CAS
BA0
A0
A3
RAS
BA1
A1
A2
WE
CS
A10
VDD
DQMH CLK
NC
A8
GND
A11
A7
A5
PIN DESCRIPTIONS
A0-A11
A0-A7
BA0, BA1
dQ0 to dQ15
CLK
CKe
CS
RAS
CAS
Row Address Input
Column Address Input
Bank Select Addresses
data I/o
System Clock Input
Clock enable
Chip Select
Row Address Strobe Command
Column Address Strobe Command
WE
LdQM, UdQM
V
dd
gNd
V
ddq
gNdQ
NC
Write enable
x16 Input/output Mask
Power
ground
Power Supply for I/o Pin
ground for I/o Pin
No Connection
Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
12/17/2013
3
IS42S16400J
IS45S16400J
PIN CONFIGURATION
PACKAGE CODE: B2 60 BALL TF-BGA (Top View) (10.1 mm x 6.4 mm Body, 0.65 mm Ball Pitch)
1 2 3 4 5 6 7
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
PIN DESCRIPTIONS
A0-A11
A0-A7
BA0, BA1
DQ0 to DQ15
CLK
CKE
CS
RAS
CAS
Row Address Input
Column Address Input
Bank Select Addresses
Data I/O
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
Column Address Strobe Command
WE
LDQM, UDQM
V
dd
GND
V
ddq
GND
q
NC
Write Enable
x16 Input/Output Mask
Power
Ground
Power Supply for I/O Pin
Ground for I/O Pin
No Connection
GND DQ15
DQ14 GNDQ
DQ13 VDDQ
DQ12 DQ11
DQ10 GNDQ
DQ9 VDDQ
DQ8
NC
NC
NC
DQ0
VDD
VDDQ DQ1
GNDQ DQ2
DQ4
DQ3
VDDQ DQ5
GNDQ DQ6
NC
VDD
LDQM
RAS
NC
BA1
A0
A2
A3
DQ7
NC
WE
CAS
CS
BA0
A10
A1
VDD
NC UDQM
NC
CKE
A11
A8
A6
GND
CLK
NC
A9
A7
A5
A4
4
Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
12/17/2013
IS42S16400J
IS45S16400J
PIN CONFIGURATIONS
54 pin TSOP - Type II
V
DD
DQ0
V
DD
Q
DQ1
DQ2
GNDQ
DQ3
DQ4
V
DD
Q
DQ5
DQ6
GNDQ
DQ7
V
DD
LDQM
WE
CAS
RAS
CS
BA0
BA1
A10
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
GND
DQ15
GNDQ
DQ14
DQ13
V
DD
Q
DQ12
DQ11
GNDQ
DQ10
DQ9
V
DD
Q
DQ8
GND
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
GND
PIN DESCRIPTIONS
A0-A11
A0-A7
BA0, BA1
DQ0 to DQ15
CLK
CKE
CS
RAS
CAS
Row Address Input
Column Address Input
Bank Select Address
Data I/O
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
Column Address Strobe Command
WE
LDQM
UDQM
V
dd
GND
V
ddq
GND
q
NC
Write Enable
x16 Lower Byte, Input/Output Mask
x16 Upper Byte, Input/Output Mask
Power
Ground
Power Supply for I/O Pin
Ground for I/O Pin
No Connection
Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
12/17/2013
5
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