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IS42S81600A, IS42LS81600A

IS42S16800A, IS42LS16800A

IS42S32400A, IS42LS32400A

16Meg x 8, 8Meg x16 & 4Meg x 32

128-MBIT SYNCHRONOUS DRAM

FEATURES

• Clock frequency: 133 100, MHz

• Fully synchronous; all signals referenced to a

positive clock edge

• Internal bank for hiding row access/precharge

• Power supply

IS42LS81600A

IS42LS16800A

IS42LS32400A

IS42S81600A

IS42S16800A

IS42S32400A

• LVTTL interface

• Programmable burst length

– (1, 2, 4, 8, full page)

• Programmable burst sequence:

Sequential/Interleave

• Extended Mode Register

• Programmable Power Reduction Feature by

partial array activation during Self-Refresh

• Auto Refresh (CBR)

• Temp. Compensated Self Refresh.

• Self Refresh with programmable refresh periods

• 4096 refresh cycles every 64 ms

• Random column address every clock cycle

• Programmable

CAS

latency (2, 3 clocks)

• Burst read/write and burst read/single write

operations capability

• Burst termination by burst stop and precharge

command

• Industrial Temperature Availability

DDQ

2.5V 1.8V (2.5V tolerant)

3.3V 3.3V

IS42LS81600A

IS42S81600A

4M x8x4 Banks

54pin TSOPII

ISSI

ADVANCED INFORMATION

AUGUST 2002

OVERVIEW

ISSI

's 128Mb Synchronous DRAM achieves high-speed

data transfer using pipeline architecture. All inputs and

outputs signals refer to the rising edge of the clock

input.The 128Mb SDARM is organized as follows.

IS42LS16800A

IS42S16800A

2M x16x4 Banks

54ball FBGA

54 pin TSOPII

IS42LS32400A

IS42S32400A

2M x16x4 Banks

90ball FBGA

86pin TSOPII

KEY TIMING PARAMETERS

Parameter

Clk Cycle Time

CAS

Latency = 3

CAS

Latency = 2

Clk Frequency

CAS

Latency = 3

CAS

Latency = 2

Access Time from Clock

CAS

Latency = 3

CAS

Latency = 2

Row to Column Delay Time (t

RCD

)

Row Precharge Tim (t

)

-7

133

100

5.4

-10

100

Unit

Mhz

time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are

advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. — www.issi.com —

1-800-379-4774

ADVANCED INFORMATION, Rev. 00A

08/01/02

IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

DEVICE OVERVIEW

The 128Mb SDRAM is a high speed CMOS, dynamic

random-access memory designed to operate in 2.5V V

and 1.8V V

DDQ

or 3.3V

and 3.3V V

DDQ

memory systems

containing 134,217 ,728 bits. Internally configured as a

quad-bank DRAM with a synchronous interface. Each

16,777,216-bit bank is organized as 4,096 rows by 256

columns by 16 bits.

The 128Mb SDRAM includes an AUTO REFRESH MODE,

and a power-saving, power-down mode. All signals are

registered on the positive edge of the clock signal, CLK. All

inputs and outputs are LVTTL compatible.

Only partials of the memory array can be selected for Self-

Refresh and the refresh period during Self-Refresh is

progammable in 4 steps which drastically reduces the self

refresh current, depending on the case temperature of the

components in the system application.

The 128Mb SDRAM has the ability to synchronously burst

data at a high data rate with automatic column-address

generation, the ability to interleave between internal banks

ISSI

to hide precharge time and the capability to randomly

change column addresses on each clock cycle during burst

access.

A self-timed row precharge initiated at the end of the burst

sequence is available with the AUTO PRECHARGE func-

tion enabled. Precharge one bank while accessing one of the

other three banks will hide the precharge cycles and provide

seamless, high-speed, random-access operation.

SDRAM read and write accesses are burst oriented starting at

a selected location and continuing for a programmed num-

ber of locations in a programmed sequence. The registra-

tion of an ACTIVE command begins accesses, followed by

a READ or WRITE command. The ACTIVE command in

conjunction with address bits registered are used to select

the bank and row to be accessed (BA0, BA1 select the

bank; A0-A11 select the row). The READ or WRITE

commands in conjunction with address bits registered are

used to select the starting column location for the burst

access.

Programmable READ or WRITE burst lengths consist of 1,

2, 4 and 8 locations or full page, with a burst terminate

option.

FUNCTIONAL BLOCK DIAGRAM

CLK

CKE

RAS

CAS

A11

DQM

COMMAND

DECODER

CLOCK

GENERATOR

DATA IN

BUFFER

MODE

REFRESH

CONTROLLER

I/O 0-15

SELF

REFRESH

CONTROLLER

A10

BA0

BA1

DATA OUT

BUFFER

Vcc/Vcc

GND/GNDQ

REFRESH

COUNTER

4096

ROW DECODER

MULTIPLEXER

MEMORY CELL

ARRAY

ROW

ADDRESS

LATCH

ROW

ADDRESS

BUFFER

BANK 0

SENSE AMP I/O GATE

COLUMN

ADDRESS LATCH

256K

(x 16)

BANK CONTROL LOGIC

BURST COUNTER

COLUMN DECODER

COLUMN

ADDRESS BUFFER

Integrated Silicon Solution, Inc. — www.issi.com —

1-800-379-4774

ADVANCED INFORMATION Rev. 00A

06/01/02

IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

PIN CONFIGURATIONS

54 pin TSOP - Type II for x8

ISSI

I/O0

I/O1

I/O2

I/O3

CAS

RAS

BA0

BA1

A10

I/O7

I/O6

I/O5

I/O4

DQM

CLK

CKE

A11

PIN DESCRIPTIONS

A0-A11

A0-A8, A10

BA0, BA1

I/O0 to I/O7

CLK

CKE

RAS

CAS

Row Address Input

Column Address Input

Bank Select Address

Data I/O

System Clock Input

Clock Enable

Chip Select

Row Address Strobe Command

Column Address Strobe Command

DQM

Vss

DDQ

Vss

Write Enable

x 8 Lower Bye, Input/Output Mask

Power

Ground

Power Supply for I/O Pin

Ground for I/O Pin

No Connection

Integrated Silicon Solution, Inc. — www.issi.com —

1-800-379-4774

ADVANCED INFORMATION Rev. 00A

06/01/02

IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

PIN CONFIGURATIONS

54-Ball FBGA for x16

ISSI

Vss

I/O14

I/O12

I/O10

I/O8

UDQM

NC/A12

Vss

A10

A11

BA0

BA1

CLK

CKE

CAS

RAS

Vss

VDD

LDQM

I/O7

I/O9

VDDQ

VssQ

I/O6

I/O5

I/O11

VssQ

VDDQ

I/O4

I/O3

I/O13

VDDQ

VssQ

I/O2

I/O1

I/O15

VssQ

VDDQ

I/O0

VDD

PIN DESCRIPTIONS

A0-A11

A0-A8, A10

BA0, BA1

DQ0 to DQ15

CLK

CKE

RAS

CAS

Row Address Input

Column Address Input

Bank Select Address

Data I/O

System Clock Input

Clock Enable

Chip Select

Row Address Strobe Command

Column Address Strobe Command

LDQM

UDQM

Vss

DDQ

Vss

Write Enable

x16 Lower Bye, Input/Output Mask

x16 Upper Bye, Input/Output Mask

Power

Ground

Power Supply for I/O Pin

Ground for I/O Pin

No Connection

Integrated Silicon Solution, Inc. — www.issi.com —

1-800-379-4774

ADVANCED INFORMATION Rev. 00A

06/01/02

IS42S81600A, IS42S16800A, IS42S32400A

IS42LS81600A, IS42LS16800A, IS42LS32400A

PIN CONFIGURATIONS

54 pin TSOP - Type II for x16

ISSI

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

LDQM

CAS

RAS

BA0

BA1

A10

I/O15

I/O14

I/O13

I/O12

I/O11

I/O10

I/O9

I/O8

UDQM

CLK

CKE

A11

PIN DESCRIPTIONS

A0-A11

A0-A8, A10

BA0, BA1

I/O0 to I/O15

CLK

CKE

RAS

CAS

Row Address Input

Column Address Input

Bank Select Address

Data I/O

System Clock Input

Clock Enable

Chip Select

Row Address Strobe Command

Column Address Strobe Command

LDQM

UDQM

Vss

DDQ

Vss

Write Enable

x16 Lower Bye, Input/Output Mask

x16 Upper Bye, Input/Output Mask

Power

Ground

Power Supply for I/O Pin

Ground for I/O Pin

No Connection

Integrated Silicon Solution, Inc. — www.issi.com —

1-800-379-4774

ADVANCED INFORMATION Rev. 00A

06/01/02