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IS42S32400E-6TLI

Synchronous DRAM, 4MX32, 5.4ns, CMOS, PDSO86, 0.400 INCH, LEAD FREE, TSOP2-86

器件类别：存储    存储   

厂商名称：Integrated Silicon Solution ( ISSI )

器件标准：  

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器件参数
参数名称
属性值
是否无铅
不含铅
是否Rohs认证
符合
厂商名称
Integrated Silicon Solution ( ISSI )
零件包装代码
TSOP2
包装说明
TSOP2, TSSOP86,.46,20
针数
86
Reach Compliance Code
compliant
ECCN代码
EAR99
访问模式
FOUR BANK PAGE BURST
最长访问时间
5.4 ns
其他特性
AUTO/SELF REFRESH
最大时钟频率 (fCLK)
166 MHz
I/O 类型
COMMON
交错的突发长度
1,2,4,8
JESD-30 代码
R-PDSO-G86
JESD-609代码
e3
长度
22.22 mm
内存密度
134217728 bit
内存集成电路类型
SYNCHRONOUS DRAM
内存宽度
32
湿度敏感等级
3
功能数量
1
端口数量
1
端子数量
86
字数
4194304 words
字数代码
4000000
工作模式
SYNCHRONOUS
最高工作温度
85 °C
最低工作温度
-40 °C
组织
4MX32
输出特性
3-STATE
封装主体材料
PLASTIC/EPOXY
封装代码
TSOP2
封装等效代码
TSSOP86,.46,20
封装形状
RECTANGULAR
封装形式
SMALL OUTLINE, THIN PROFILE
峰值回流温度（摄氏度）
260
电源
3.3 V
认证状态
Not Qualified
刷新周期
4096
座面最大高度
1.2 mm
自我刷新
YES
连续突发长度
1,2,4,8,FP
最大待机电流
0.001 A
最大压摆率
0.18 mA
最大供电电压 (Vsup)
3.6 V
最小供电电压 (Vsup)
3 V
标称供电电压 (Vsup)
3.3 V
表面贴装
YES
技术
CMOS
温度等级
INDUSTRIAL
端子面层
Matte Tin (Sn) - annealed
端子形式
GULL WING
端子节距
0.5 mm
端子位置
DUAL
处于峰值回流温度下的最长时间
10
宽度
10.16 mm
文档预览
IS42S32400E
4M x 32
128Mb SYNCHRONOUS DRAM
PRELIMINARY INFORMATION
AUGUST 2008
FEATURES
• Clock frequency: 166, 143 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Internal bank for hiding row access/precharge
• Power supply
IS42S32400E
• LVTTL interface
• Programmable burst length
– (1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• Auto Refresh (CBR)
• Self Refresh
• 4096 refresh cycles every 64 ms
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
operations capability
• Burst termination by burst stop and precharge
command
• Available in Industrial Temperature
• Available in 86-pin TSOP-II and 90-ball FBGA
• Available in Lead-free
V
dd
V
ddq
3.3V 3.3V
OVERVIEW
ISSI
's 128Mb Synchronous DRAM achieves high-speed
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock input.
The 128Mb SDRAM is organized in 1Meg x 32 bit x 4
Banks.
KEY TIMING PARAMETERS
Parameter
Clk Cycle Time
CAS Latency = 3
CAS Latency = 2
Clk Frequency
CAS Latency = 3
CAS Latency = 2
Access Time from Clock
CAS Latency = 3
CAS Latency = 2
-6
6
8
166
125
5.4
6.5
-7
7
10
143
100
5.4
6.5
Unit
ns
ns
Mhz
Mhz
ns
ns
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time with-
out notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain
the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc.
- www.issi.com
Rev. 00C
08/01/08
1
IS42S32400E
DEVICE OVERVIEW
The 128Mb SDRAM is a high speed CMOS, dynamic
random-access memory designed to operate in 3.3V V
dd
and 3.3V V
ddq
memory systems containing 134,217,728
bits. Internally configured as a quad-bank DRAM with a
synchronous interface. Each 33,554,432-bit bank is orga-
nized as 4,096 rows by 256 columns by 32 bits.
The 128Mb SDRAM includes an AUTO REFRESH MODE,
and a power-saving, power-down mode. All signals are
registered on the positive edge of the clock signal, CLK.
All inputs and outputs are LVTTL compatible.
The 128Mb SDRAM has the ability to synchronously burst
data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks
to hide precharge time and the capability to randomly
change column addresses on each clock cycle during
burst access.
A self-timed row precharge initiated at the end of the burst
sequence is available with the AUTO PRECHARGE function
enabled.
Precharge
one bank while accessing one of the
other three banks will hide the precharge cycles and provide
seamless, high-speed, random-access operation.
SDRAM
read and write accesses are burst oriented starting
at a selected location and continuing for a programmed
number of locations in a programmed sequence. The
registration of an ACTIVE command begins accesses,
followed by a READ or WRITE command. The ACTIVE
command in conjunction with address bits registered are
used to select the bank and row to be accessed (BA0,
BA1 select the bank; A0-A11 select the row). The READ
or WRITE commands in conjunction with address bits
registered are used to select the starting column location
for the burst access.
Programmable READ or WRITE burst lengths consist of
1, 2, 4 and 8 locations or full page, with a burst terminate
option.
FUNCTIONAL BLOCK DIAGRAM (FOR 1MX32X4
BANKS)
CLK
CKE
CS
RAS
CAS
WE
DQM0 - DQM3
COMMAND
DECODER
&
CLOCK
GENERATOR
DATA IN
BUFFER
32
32
4
MODE
REGISTER
12
REFRESH
CONTROLLER
DQ 0-31
SELF
REFRESH
CONTROLLER
A10
A11
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA0
BA1
12
32
DATA OUT
BUFFER
V
DD
/V
DDQ
V
ss
/V
ss
Q
32
REFRESH
COUNTER
4096
4096
4096
4096
ROW DECODER
MULTIPLEXER
12
MEMORY CELL
ARRAY
ROW
ADDRESS
LATCH
12
ROW
ADDRESS
BUFFER
BANK 0
SENSE AMP I/O GATE
COLUMN
ADDRESS LATCH
8
256
(x 32)
BANK CONTROL LOGIC
BURST COUNTER
COLUMN
ADDRESS BUFFER
COLUMN DECODER
8
2
Integrated Silicon Solution, Inc.
- www.issi.com
Rev. 00C
08/01/08
IS42S32400E
PIN CONFIGURATIONS
86 pin TSOP - Type II for x32
V
DD
DQ0
V
DD
Q
DQ1
DQ2
V
SS
Q
DQ3
DQ4
V
DD
Q
DQ5
DQ6
V
SS
Q
DQ7
NC
V
DD
DQM0
WE
CAS
RAS
CS
A11
BA0
BA1
A10
A0
A1
A2
DQM2
V
DD
NC
DQ16
V
SS
Q
DQ17
DQ18
V
DD
Q
DQ19
DQ20
V
SS
Q
DQ21
DQ22
V
DD
Q
DQ23
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
V
SS
DQ15
V
SS
Q
DQ14
DQ13
V
DD
Q
DQ12
DQ11
V
SS
Q
DQ10
DQ9
V
DD
Q
DQ8
NC
V
SS
DQM1
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
V
SS
NC
DQ31
V
DD
Q
DQ30
DQ29
V
SS
Q
DQ28
DQ27
V
DD
Q
DQ26
DQ25
V
SS
Q
DQ24
V
SS
PIN DESCRIPTIONS
A0-A11
A0-A7
BA0, BA1
DQ0 to DQ31
CLK
CKE
CS
RAS
CAS
Row Address Input
Column Address Input
Bank Select Address
Data I/O
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
Column Address Strobe Command
WE
DQM0-DQM3
V
dd
Vss
V
ddq
Vss
q
NC
Write Enable
x32 Input/Output Mask
Power
Ground
Power Supply for I/O Pin
Ground for I/O Pin
No Connection
Integrated Silicon Solution, Inc.
- www.issi.com
Rev. 00C
08/01/08
3
IS42S32400E
PIN CONFIGURATION
PACKAGE CODE: B 90 BALL FBGA (Top View) (8.00 mm x 13.00 mm Body, 0.8 mm Ball Pitch)
1 2 3 4 5 6 7 8 9
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
PIN DESCRIPTIONS
A0-A11
A0-A7
BA0, BA1
DQ0 to DQ31
CLK
CKE
CS
RAS
CAS
Row Address Input
Column Address Input
Bank Select Address
Data I/O
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
Column Address Strobe Command
WE
DQM0-DQM3
V
dd
Vss
V
ddq
Vss
q
NC
Write Enable
x32 Input/Output Mask
Power
Ground
Power Supply for I/O Pin
Ground for I/O Pin
No Connection
DQ26 DQ24
VSS
VDD DQ23 DQ21
VDDQ VSSQ DQ19
DQ22 DQ20 VDDQ
DQ17 DQ18 VDDQ
NC
A2
A10
NC
BA0
CAS
VDD
DQ6
DQ1
DQ16 VSSQ
DQM2 VDD
A0
BA1
CS
A1
A11
RAS
DQ28 VDDQ VSSQ
VSSQ DQ27 DQ25
VSSQ DQ29 DQ30
VDDQ DQ31
VSS DQM3
A4
A7
CLK
DQM1
A5
A8
CKE
NC
NC
A3
A6
NC
A9
NC
VSS
WE
DQM0
DQ7 VSSQ
DQ5 VDDQ
DQ3 VDDQ
VDDQ DQ8
VSSQ DQ10 DQ9
VSSQ DQ12 DQ14
DQ11 VDDQ VSSQ
DQ13 DQ15
VSS
VDDQ VSSQ DQ4
VDD
DQ0
DQ2
4
Integrated Silicon Solution, Inc.
- www.issi.com
Rev. 00C
08/01/08
IS42S32400E
PIN FUNCTIONS
Symbol
A0-A11
Type
Input Pin
Function (In Detail)
Address Inputs: A0-A11 are sampled during the ACTIVE
command (row-address A0-A11) and READ/WRITE command (column address
A0-A7), with A10 defining auto precharge) to select one location out of the memory
array in the respective bank. A10 is sampled during a PRECHARGE command to
determine if all banks are to be precharged (A10 HIGH) or bank selected by
BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD
MODE REGISTER command.
Bank Select Address: BA0 and BA1 defines which bank the ACTIVE, READ, WRITE
or PRECHARGE command is being applied.
CAS,
in conjunction with the
RAS
and
WE,
forms the device command. See the
"Command Truth Table" for details on device commands.
The CKE input determines whether the CLK input is enabled. The next rising edge
of the CLK signal will be valid when is CKE HIGH and invalid when LOW. When CKE
is LOW, the device will be in either power-down mode, clock suspend mode, or self
refresh mode.
CKE is an
asynchronous input.
CLK is the master clock input for this device. Except for CKE, all inputs to this device
are acquired in synchronization with the rising edge of this pin.
The CS
input determines whether command input is enabled within the device.
Command input is enabled when
CS is LOW, and disabled with CS is HIGH. The
device remains in the previous state when
CS is HIGH.
DQM0 - DQM3 control the four bytes of the I/O buffers (DQ0-DQ31). In read
mode, DQMn control the output buffer. When DQMn is LOW, the corresponding buf-
fer byte is enabled, and when HIGH, disabled. The outputs go to the HIGH imped-
ance state whenDQMn is HIGH. This function corresponds to OE
in conventional
DRAMs. In write mode, DQMn control the input buffer. When DQMn is LOW, the
corresponding buffer byte is enabled, and data can be written to the device. When
DQMn is HIGH, input data is masked and cannot be written to the device.
Data on the Data Bus is latched on these pins during Write commands, and buffered after
Read commands.
RAS,
in conjunction with
CAS
and
WE,
forms the device command. See the "Com-
mand Truth Table" item for details on device commands.
WE,
in conjunction with
RAS
and
CAS,
forms the device command. See the "Com-
mand Truth Table" item for details on device commands.
V
ddq
is the output buffer power supply.
V
dd
is the device internal power supply.
V
ssq
is the output buffer ground.
V
ss
is the device internal ground.
BA0, BA1
CAS
CKE
Input Pin
Input Pin
Input Pin
CLK
CS
Input Pin
Input Pin
D
QM0-DQM3
Input Pin
DQ0-DQ31
RAS
WE
V
ddq
V
dd
V
ssq
V
ss
I
nput/Output Pin
Input Pin
Input Pin
P
ower Supply Pin
P
ower Supply Pin
P
ower Supply Pin
P
ower Supply Pin
Integrated Silicon Solution, Inc.
- www.issi.com
Rev. 00C
08/01/08
5
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参数对比
与IS42S32400E-6TLI相近的元器件有：IS42S32400E-7TL、IS42S32400E-7TLI、IS42S32400E-7TLI-TR、IS42S32400E-7TL-TR、IS42S32400E-6TL、IS42S32400E-6BL、IS42S32400E-7BLI、IS42S32400E-7BL。描述及对比如下：
型号 IS42S32400E-6TLI IS42S32400E-7TL IS42S32400E-7TLI IS42S32400E-7TLI-TR IS42S32400E-7TL-TR IS42S32400E-6TL IS42S32400E-6BL IS42S32400E-7BLI IS42S32400E-7BL
描述 Synchronous DRAM, 4MX32, 5.4ns, CMOS, PDSO86, 0.400 INCH, LEAD FREE, TSOP2-86 Synchronous DRAM, 4MX32, 5.4ns, CMOS, PDSO86, 0.400 INCH, LEAD FREE, TSOP2-86 Synchronous DRAM, 4MX32, 5.4ns, CMOS, PDSO86, 0.400 INCH, LEAD FREE, TSOP2-86 Synchronous DRAM, 4MX32, 5.4ns, CMOS, PDSO86, 0.400 INCH, LEAD FREE, TSOP2-86 Synchronous DRAM, 4MX32, 5.4ns, CMOS, PDSO86, 0.400 INCH, LEAD FREE, TSOP2-86 Synchronous DRAM, 4MX32, 5.4ns, CMOS, PDSO86, 0.400 INCH, LEAD FREE, TSOP2-86 Synchronous DRAM, 4MX32, 5.4ns, CMOS, PBGA90, 8 X 13 MM, 0.80 MM PITCH, LEAD FREE, FBGA-90 Synchronous DRAM, 4MX32, 5.4ns, CMOS, PBGA90, 8 X 13 MM, 0.80 MM PITCH, LEAD FREE, FBGA-90 Synchronous DRAM, 4MX32, 5.4ns, CMOS, PBGA90, 8 X 13 MM, 0.80 MM PITCH, LEAD FREE, FBGA-90
是否Rohs认证 符合 符合 符合 符合 符合 符合 符合 符合 符合
包装说明 TSOP2, TSSOP86,.46,20 TSOP2, TSSOP86,.46,20 TSOP2, TSSOP86,.46,20 TSOP2, TSSOP, TSOP2, TSSOP86,.46,20 TFBGA, BGA90,9X15,32 TFBGA, BGA90,9X15,32 TFBGA, BGA90,9X15,32
Reach Compliance Code compliant compli compli compli compliant compliant compliant compliant compliant
ECCN代码 EAR99 EAR99 EAR99 EAR99 EAR99 EAR99 EAR99 EAR99 EAR99
访问模式 FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST
最长访问时间 5.4 ns 5.4 ns 5.4 ns 5.4 ns 5.4 ns 5.4 ns 5.4 ns 5.4 ns 5.4 ns
其他特性 AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH
JESD-30 代码 R-PDSO-G86 R-PDSO-G86 R-PDSO-G86 R-PDSO-G86 R-PDSO-G86 R-PDSO-G86 R-PBGA-B90 R-PBGA-B90 R-PBGA-B90
JESD-609代码 e3 e3 e3 e3 e3 e3 e1 e1 e1
长度 22.22 mm 22.22 mm 22.22 mm 22.22 mm 22.22 mm 22.22 mm 13 mm 13 mm 13 mm
内存密度 134217728 bit 134217728 bi 134217728 bi 134217728 bi 134217728 bit 134217728 bit 134217728 bit 134217728 bit 134217728 bit
内存集成电路类型 SYNCHRONOUS DRAM SYNCHRONOUS DRAM SYNCHRONOUS DRAM SYNCHRONOUS DRAM SYNCHRONOUS DRAM SYNCHRONOUS DRAM SYNCHRONOUS DRAM SYNCHRONOUS DRAM SYNCHRONOUS DRAM
内存宽度 32 32 32 32 32 32 32 32 32
湿度敏感等级 3 3 3 3 3 3 3 3 3
功能数量 1 1 1 1 1 1 1 1 1
端口数量 1 1 1 1 1 1 1 1 1
端子数量 86 86 86 86 86 86 90 90 90
字数 4194304 words 4194304 words 4194304 words 4194304 words 4194304 words 4194304 words 4194304 words 4194304 words 4194304 words
字数代码 4000000 4000000 4000000 4000000 4000000 4000000 4000000 4000000 4000000
工作模式 SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS
最高工作温度 85 °C 70 °C 85 °C 85 °C 70 °C 70 °C 70 °C 85 °C 70 °C
组织 4MX32 4MX32 4MX32 4MX32 4MX32 4MX32 4MX32 4MX32 4MX32
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 TSOP2 TSOP2 TSOP2 TSOP2 TSSOP TSOP2 TFBGA TFBGA TFBGA
封装形状 RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
封装形式 SMALL OUTLINE, THIN PROFILE SMALL OUTLINE, THIN PROFILE SMALL OUTLINE, THIN PROFILE SMALL OUTLINE, THIN PROFILE SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE GRID ARRAY, THIN PROFILE, FINE PITCH GRID ARRAY, THIN PROFILE, FINE PITCH GRID ARRAY, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度） 260 260 260 260 260 260 260 260 260
座面最大高度 1.2 mm 1.2 mm 1.2 mm 1.2 mm 1.2 mm 1.2 mm 1.2 mm 1.2 mm 1.2 mm
自我刷新 YES YES YES YES YES YES YES YES YES
最大供电电压 (Vsup) 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V
最小供电电压 (Vsup) 3 V 3 V 3 V 3 V 3 V 3 V 3 V 3 V 3 V
标称供电电压 (Vsup) 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
表面贴装 YES YES YES YES YES YES YES YES YES
技术 CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
温度等级 INDUSTRIAL COMMERCIAL INDUSTRIAL INDUSTRIAL COMMERCIAL COMMERCIAL COMMERCIAL INDUSTRIAL COMMERCIAL
端子面层 Matte Tin (Sn) - annealed Matte Tin (Sn) - annealed Matte Tin (Sn) - annealed Matte Tin (Sn) Matte Tin (Sn) Matte Tin (Sn) - annealed Tin/Silver/Copper (Sn/Ag/Cu) Tin/Silver/Copper (Sn/Ag/Cu) Tin/Silver/Copper (Sn/Ag/Cu)
端子形式 GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING BALL BALL BALL
端子节距 0.5 mm 0.5 mm 0.5 mm 0.5 mm 0.5 mm 0.5 mm 0.8 mm 0.8 mm 0.8 mm
端子位置 DUAL DUAL DUAL DUAL DUAL DUAL BOTTOM BOTTOM BOTTOM
处于峰值回流温度下的最长时间 10 10 10 40 10 10 10 10 10
宽度 10.16 mm 10.16 mm 10.16 mm 10.16 mm 10.16 mm 10.16 mm 8 mm 8 mm 8 mm
是否无铅 不含铅 不含铅 不含铅 不含铅 - 不含铅 不含铅 不含铅 不含铅
厂商名称 Integrated Silicon Solution ( ISSI ) - - - Integrated Silicon Solution ( ISSI ) Integrated Silicon Solution ( ISSI ) Integrated Silicon Solution ( ISSI ) Integrated Silicon Solution ( ISSI ) Integrated Silicon Solution ( ISSI )
零件包装代码 TSOP2 TSOP2 TSOP2 TSOP2 - TSOP2 BGA BGA BGA
针数 86 86 86 86 - 86 90 90 90
最大时钟频率 (fCLK) 166 MHz 143 MHz 143 MHz - - 166 MHz 166 MHz 143 MHz 143 MHz
I/O 类型 COMMON COMMON COMMON - - COMMON COMMON COMMON COMMON
交错的突发长度 1,2,4,8 1,2,4,8 1,2,4,8 - - 1,2,4,8 1,2,4,8 1,2,4,8 1,2,4,8
输出特性 3-STATE 3-STATE 3-STATE - - 3-STATE 3-STATE 3-STATE 3-STATE
封装等效代码 TSSOP86,.46,20 TSSOP86,.46,20 TSSOP86,.46,20 - - TSSOP86,.46,20 BGA90,9X15,32 BGA90,9X15,32 BGA90,9X15,32
电源 3.3 V 3.3 V 3.3 V - - 3.3 V 3.3 V 3.3 V 3.3 V
认证状态 Not Qualified Not Qualified Not Qualified Not Qualified - Not Qualified Not Qualified Not Qualified Not Qualified
刷新周期 4096 4096 4096 - - 4096 4096 4096 4096
连续突发长度 1,2,4,8,FP 1,2,4,8,FP 1,2,4,8,FP - - 1,2,4,8,FP 1,2,4,8,FP 1,2,4,8,FP 1,2,4,8,FP
最大待机电流 0.001 A 0.001 A 0.001 A - - 0.001 A 0.001 A 0.001 A 0.001 A
最大压摆率 0.18 mA 0.16 mA 0.16 mA - - 0.18 mA 0.18 mA 0.16 mA 0.16 mA
TMS320F28035学习记录五
IQMath lib的使用 参考手册《IQmath_Quickstart.pdf》 版本V1.6...
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