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IS42S16800L

IS42S32400L

8Meg x16 & 4Meg x 32 (128-MBIT)

PowerSaver SYNC DYNAMIC RAM

FEATURES

• Clock frequency: 143, 100, MHz

• Fully synchronous; all signals referenced to a

positive clock edge

• Internal bank for hiding row access/precharge

• Power supply

= 2.5V/ +/-10%

q= 1.8V (2.5V tolerant)

• LVTTL interface

• Programmable burst length

– (1, 2, 4, 8, full page)

• Programmable burst sequence:

Sequential/Interleave

• Extended Mode Register

• Programmable Power Reduction Feature by

partial array activation during Self-Refresh

• Auto Refresh (CBR)

• Temp. Compensated Self Refresh.

• Self Refresh with programmable refresh periods

• 4096 refresh cycles every 64 ms

• Random column address every clock cycle

• Programmable

CAS

latency (2, 3 clocks)

• Burst read/write and burst read/single write

operations capability

• Burst termination by burst stop and precharge

command

• Industrial Temperature Availability

• Bare and Known Good Die

Package:

ISSI

ADVANCED INFORMATION

SEPTEMBER 2002

OVERVIEW

ISSI

's 128Mb Synchronous DRAM IS42S16800L is

organized as 2Meg x16 x 4 banks (8 Meg x16) and the

IS42S32400L is organized as 1Meg x32 x 4 banks (4Meg x

32) . The synchronous DRAMs achieve high-speed data

transfer using pipeline architecture. All inputs and outputs

signals refer to the rising edge of the clock input.

54-Ball FBGA for x16

54 Pin TSOPII for x16

90-Ball FBGA for x32

86-Pin TSOPII for x32

KEY TIMING PARAMETERS

Parameter

Clk Cycle Time

CAS

Latency = 3

CAS

Latency = 2

Clk Frequency

CAS

Latency = 3

CAS

Latency = 2

Access Time from Clock

CAS

Latency = 3

CAS

Latency = 2

Row to Column Delay Time (t

RCD

)

Row Precharge Tim (t

)

-7

143

100

5.4

-10

100

Unit

Mhz

time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are

advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. — www.issi.com —

1-800-379-4774

Rev. 00B

09/24/02

IS42S16800L, IS42S32400L

DEVICE OVERVIEW

The 128Mb SDRAM is a high speed CMOS, dynamic

random-access memory designed to operate in 2.5V

and

1.8V V

DDQ

memory systems containing 134,217 ,728 bits.

Internally configured as a quad-bank DRAM with a synchro-

nous interface. Each 16,777,216-bit bank is organized as

4,096 rows by 256 columns by 16 bits.

The 128Mb SDRAM includes an AUTO REFRESH MODE,

and a power-saving, power-down mode. All signals are

registered on the positive edge of the clock signal, CLK. All

inputs and outputs are LVTTL compatible.

Only partials of the memory array can be selected for Self-

Refresh and the refresh period during Self-Refresh is

progammable in 4 steps which drastically reduces the selft

refresh current, depending on the case temperature of the

components in the system applciation.

The 128Mb SDRAM has the ability to synchronously burst

data at a high data rate with automatic column-address

generation, the ability to interleave between internal banks

to hide precharge time and the capability to randomly

ISSI

change column addresses on each clock cycle during burst

access.

A self-timed row precharge initiated at the end of the burst

sequence is available with the AUTO PRECHARGE func-

tion enabled. Precharge one bank while accessing one of the

other three banks will hide the precharge cycles and provide

seamless, high-speed, random-access operation.

SDRAM read and write accesses are burst oriented starting at

a selected location and continuing for a programmed num-

ber of locations in a programmed sequence. The registra-

tion of an ACTIVE command begins accesses, followed by

a READ or WRITE command. The ACTIVE command in

conjunction with address bits registered are used to select

the bank and row to be accessed (BA0, BA1 select the

bank; A0-A11 select the row). The READ or WRITE

commands in conjunction with address bits registered are

used to select the starting column location for the burst

access.

Programmable READ or WRITE burst lengths consist of 1,

2, 4 and 8 locations or full page, with a burst terminate

option.

FUNCTIONAL BLOCK DIAGRAM

CLK

CKE

RAS

CAS

A11

DQM

COMMAND

DECODER

CLOCK

GENERATOR

DATA IN

BUFFER

MODE

REFRESH

CONTROLLER

I/O 0-15

SELF

REFRESH

CONTROLLER

A10

BA0

BA1

DATA OUT

BUFFER

Vcc/Vcc

GND/GNDQ

REFRESH

COUNTER

4096

ROW DECODER

MULTIPLEXER

MEMORY CELL

ARRAY

ROW

ADDRESS

LATCH

ROW

ADDRESS

BUFFER

BANK 0

SENSE AMP I/O GATE

COLUMN

ADDRESS LATCH

256K

(x 16)

BANK CONTROL LOGIC

BURST COUNTER

COLUMN DECODER

COLUMN

ADDRESS BUFFER

Integrated Silicon Solution, Inc. — www.issi.com —

1-800-379-4774

Rev. 00B

09/24/02

IS42S16800L, IS42S32400L

PIN CONFIGURATIONS

54-Ball FBGA

ISSI

Vss

I/O14

I/O12

I/O10

I/O8

UDQM

NC/A12

Vss

A10

A11

BA0

BA1

CLK

CKE

CAS

RAS

Vss

VDD

LDQM

I/O7

I/O9

VDDQ

VssQ

I/O6

I/O5

I/O11

VssQ

VDDQ

I/O4

I/O3

I/O13

VDDQ

VssQ

I/O2

I/O1

I/O15

VssQ

VDDQ

I/O0

VDD

PIN DESCRIPTIONS

A0-A11

A0-A8, A10

BA0, BA1

I/O0 to I/O15

CLK

CKE

RAS

CAS

Row Address Input

Column Address Input

Bank Select Address

Data I/O

System Clock Input

Clock Enable

Chip Select

Row Address Strobe Command

Column Address Strobe Command

LDQM

UDQM

Vss

DDQ

Vss

Write Enable

x16 Lower Bye, Input/Output Mask

x16 Upper Bye, Input/Output Mask

Power

Ground

Power Supply for I/O Pin

Ground for I/O Pin

No Connection

Integrated Silicon Solution, Inc. — www.issi.com —

1-800-379-4774

Rev. 00B

09/24/02

IS42S16800L, IS42S32400L

PIN CONFIGURATIONS

90-Ball FBGA

ISSI

I/O26

I/O28

VssQ

VDDQ

Vss

CLK

DQM1

VDDQ

VssQ

I/O11

I/O13

I/O24

VDDQ

I/O27

I/O29

I/O31

DQM3

CKE

I/O8

I/O10

I/O12

VDDQ

I/O15

Vss

VssQ

I/O25

I/O30

Vss

I/O9

I/O14

VssQ

Vss

VDD

VDDQ

I/O22

I/O17

A10

NC/A12

BA0

CAS

VDD

I/O6

I/O1

VDDQ

VDD

I/O23

Vss

I/O20

I/O18

I/O16

DQM2

BA1

I/O7

I/O5

I/O3

VssQ

I/O0

I/O21

I/O19

VDDQ

Vss

VDD

A11

RAS

DQM0

VssQ

VDDQ

I/O4

I/O2

PIN DESCRIPTIONS

A0-A11

A0-A8, A10

BA0, BA1

I/O0 to I/O31

CLK

CKE

RAS

CAS

Row Address Input

Column Address Input

Bank Select Address

Data I/O

System Clock Input

Clock Enable

Chip Select

Row Address Strobe Command

Column Address Strobe Command

DQM0-DQM3

Vss

DDQ

Vss

Write Enable

x32 Input/Output Mask

Power

Ground

Power Supply for I/O Pin

Ground for I/O Pin

No Connection

Integrated Silicon Solution, Inc. — www.issi.com —

1-800-379-4774

Rev. 00B

09/24/02

IS42S16800L, IS42S32400L

PIN FUNCTIONS

Symbol

A0-A11

Type

Input Pin

Function (In Detail)

ISSI

Address Inputs: A0-A11 are sampled during the ACTIVE

command (row-address A0-A11) and READ/WRITE command (A0-A7

with A10 defining auto precharge) to select one location out of the memory array

in the respective bank. A10 is sampled during a PRECHARGE command to determine if

all banks are to be precharged (A10 HIGH) or bank selected by

BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE

Bank Select Address: BA0 and BA1 defines which bank the ACTIVE, READ, WRITE or

PRECHARGE command is being applied.

CAS,

in conjunction with the

RAS

and

WE,

forms the device command. See the

"Command Truth Table" for details on device commands.

The CKE input determines whether the CLK input is enabled. The next rising edge of the

CLK signal will be valid when is CKE HIGH and invalid when LOW. When CKE is LOW,

the device will be in either power-down mode, clock suspend mode, or self refresh

mode. CKE is an asynchronous input.

CLK is the master clock input for this device. Except for CKE, all inputs to this device

are acquired in synchronization with the rising edge of this pin.

The

input determines whether command input is enabled within the device.

Command input is enabled when

is LOW, and disabled with

is HIGH. The device

remains in the previous state when

is HIGH.

I/O0 to I/O15 are I/O pins. I/O through these pins can be controlled in byte units

using the LDQM and UDQM pins.

LDQM and UDQM control the lower and upper bytes of the I/O buffers. In read

mode, LDQM and UDQM control the output buffer. When LDQM or UDQM is LOW, the

corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go to the

HIGH impedance state when LDQM/UDQM is HIGH. This function corresponds to

in conventional DRAMs. In write mode, LDQM and UDQM control the input buffer.

When LDQM or UDQM is LOW, the corresponding buffer byte is enabled, and data can

be written to the device. When LDQM or UDQM is HIGH, input data is masked and

cannot be written to the device.

RAS,

in conjunction with

CAS

and

WE,

forms the device command. See the "Command

Truth Table" item for details on device commands.

WE,

in conjunction with

RAS

and

CAS,

forms the device command. See the "Command

Truth Table" item for details on device commands.

DDQ

is the output buffer power supply.

is the device internal power supply.

SSQ

is the output buffer ground.

is the device internal ground.

BA0, BA1

CAS

CKE

Input Pin

CLK

Input Pin

I/O0 to

I/O15

LDQM,

UDQM

I/O Pin

Input Pin

RAS

DDQ

SSQ

Input Pin

Power Supply Pin

Integrated Silicon Solution, Inc. — www.issi.com —

1-800-379-4774

Rev. 00B

09/24/02

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