IS42S83200A1
(4-bank x 8,388,608 - word x 8-bit)
IS42S16160A1
(4-bank x 4,194,304 - word x 16-bit)
ISSI
October 2005
®
256 Mb Synchronous DRAM
DESCRIPTION
IS42S83200A1 is a synchronous
256Mb
SDRAM and is
organized as 4-bank x 8,388,608-word x 8-bit; and
IS42S16160A1 is organized as 4-bank x 4,194,304-word x
16-bit.
All inputs and outputs are referenced to the rising
edge of CLK.
IS42S83200A1
and
IS42S16160A1
achieve very
high speed clock rates
up to 166MHz,
and are
suitable for main memories or
graphic
memories in computer systems.
FEATURES
ITEM
tCLK
Clock Cycle Time
(Min.)
CL=2
CL=3
IS42S83200A1/16160A1
-6
-
6
42
15
CL=2
CL=3
-7
-
7
45
20
-
5.4
63
-75
10
7.5
45
20
6
5.4
67.5
110
Unit
ns
ns
ns
ns
ns
ns
ns
mA
mA
mA
tRAS Active to Precharge Command Period (Min.)
(Min.)
tRCD Row to Column Delay
tAC
tRC
Icc1
Icc6
Access Time from CLK
Ref /Active Command Period
Operation Current (Single Bank)
Self Refresh Current
(Max.)
(Min.)
(Max.)
IS42S83200A1
IS42S16160A1
-
5
60
-
130
3
-
130
3
-
3
(Max.) -6,-7,-75
- Single 3.3V ±0.3V power supply
- Max. Clock frequency:
-6:166MHz<3-3-3>
-7:143MHz<3-3-3>
-75:133MHz<3-3-3>
- Fully synchronous operation referenced to clock rising edge
- 4-bank operation controlled by BA0,BA1(Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/FP (programmable)
- Burst type- Sequential and interleave burst (programmable)
- Byte Control- DQML and DQMU (IS42S16160A1)
- Random column access
- Auto precharge / All bank precharge controlled by A10
- Auto and self refresh
- 8192 refresh cycles /64ms(4 banks concurrent refresh)
- LVTTL Interface
- Row address A0-12 /Column address A0-9(x8) / A0-8(x16)
- Package:
400-mil, 54-pin Thin Small Outline (TSOP II) with 0.8mm lead pitch
-
Lead-free available
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
10/28/05
1
IS42S83200A1
IS42S16160A1
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
ISSI
®
PIN CONFIGURATION (TOP VIEW)
x8
x16
Vdd
DQ0
VddQ
NC
DQ1
VssQ
NC
DQ2
VddQ
NC
DQ3
VssQ
NC
Vdd
NC
/WE
/CAS
/RAS
/CS
BA0
BA1
A10/AP
A0
A1
A2
A3
Vdd
Vdd
DQ0
VddQ
DQ1
DQ2
VssQ
DQ3
DQ4
VddQ
DQ5
DQ6
VssQ
DQ7
Vdd
DQML
/WE
/CAS
/RAS
/CS
BA0
BA1
A10/AP
A0
A1
A2
A3
Vdd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
Vss
DQ15
VssQ
DQ14
DQ13
VddQ
DQ12
DQ11
VssQ
DQ10
DQ9
VddQ
DQ8
Vss
NC
DQMU
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
Vss
Vss
DQ7
VssQ
NC
DQ6
VddQ
NC
DQ5
VssQ
NC
DQ4
VddQ
NC
Vss
NC
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
Vss
400mil x 875mil 54pin 0.8mm pitch TSOP(II)
CLK
CKE
/CS
/RAS
/CAS
/WE
DQ0-15
: Master Clock
: Clock Enable
: Chip Select
: Row Address Strobe
: Column Address Strobe
: Write Enable
: Data I/O
DQM, DQMU/L
A0-12
BA0,1
Vdd
VddQ
Vss
VssQ
: Output Disable / Write Mask
: Address Input
: Bank Address Input
: Power Supply
: Power Supply for Output
: Ground
: Ground for Output
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
10/28/05
IS42S83200A1
IS42S16160A1
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
ISSI
®
BLOCK DIAGRAM
DQ0-7
I/O Buffer
Memory Array
8192x1024x8
Cell Array
Memory Array
8192x1024x8
Cell Array
Memory Array
8192x1024x8
Cell Array
Memory Array
8192x1024x8
Cell Array
Bank #0
Bank #1
Bank #2
Bank #3
Mode
Register
Control Circuitry
Address Buffer
Clock Buffer
Control Signal Buffer
A0-12
BA0,1
CLK
CKE
/CS
/RAS
/CAS
/WE
DQM
Note:This figure shows the
IS42S83200A1
The IS42S16160A1 configuration is 8192x512x16 of cell array and DQ0-15
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
10/28/05
3
IS42S83200A1
IS42S16160A1
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
ISSI
®
PIN FUNCTION
CLK
Input
Master Clock:
All other inputs are referenced to the rising edge of CLK
Clock Enable:
CKE controls internal clock.When CKE is low, internal clock for
the following cycle is ceased. CKE is also used to select
auto / self-refresh.
After self-refresh mode is started, CKE becomes asynchronous input.
Self-refresh is maintained as long as CKE is low.
Chip Select:
When /CS is high, any command means No Operation.
Combination of /RAS, /CAS, /WE defines basic commands.
A0-12 specify the Row / Column Address in conjunction with BA0,1.
The Row Address is specified by A0-12.
The Column Address is specified by A0-9(x8)/A0-8(x16).
A10 is also used to indicate precharge option. When A10 is high at a
read / write command, an auto precharge is performed. When A10 is
high at a precharge command, all banks are precharged.
Bank Address:
BA0,1 specifies one of four banks to which a command is applied.
BA0,1 must be set with ACT, PRE , READ , WRITE commands.
CKE
Input
/CS
/RAS, /CAS, /WE
Input
Input
A0-12
Input
BA0,1
Input
DQ0-7(x8),
DQ0-15(x16)
DQM(x8),
DQMU/L(x16)
Vdd, Vss
VddQ, VssQ
Input / Output
Data In and Data out are referenced to the rising edge of CLK.
Din Mask / Output Disable:
When DQM(U/L) is high in burst write, Din for the current cycle is
masked. When DQM(U/L) is high in burst read,
Dout is disabled at the next but one cycle.
Power Supply for the memory array and peripheral circuitry.
Input
Power Supply
Power Supply
VddQ and VssQ are supplied to the Output Buffers only.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
10/28/05
IS42S83200A1
IS42S16160A1
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
ISSI
®
BASIC FUNCTIONS
The
IS42S83200A1/16160A1
provides basic
functions,
bank (row) activate, burst read / write, bank (row)
precharge,
and auto / self refresh.
Each command is defined by control signals of /RAS,
/CAS and /WE at CLK rising edge. In addition to 3 signals,
/CS, CKE and A10 are used as chip select, refresh opt ion,
and precharge option, respectively .
To know the detailed definition of commands,
please see the command truth table.
CLK
/CS
/RAS
/CAS
/WE
CKE
A10
Chip Select : L=select, H=deselect
Command
Command
Command
Refresh Option @ refresh command
Precharge Option @ precharge or read/write command
define basic command
Activate (ACT) [/RAS =L, /CAS =/WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read (READ) [/RAS =H, /CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA.
First output data appears after /CAS latency. When A10 =H at this command,
the bank is deactivated after the burst read (auto-precharge,
READA).
Write (WRITE) [/RAS =H, /CAS =/WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total
data length to be written is set by burst length. When A10 =H at this command,
the bank is deactivated after the burst write (auto-precharge,
WRITEA).
Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]
PRE command deactivates the active bank indicated by BA. This com
mand also terminates burst read / write operation. When A10 =H at this
command, all banks are deactivated (precharge all,
PREA
).
Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh address including bank
address are generated internally. After this command, the banks are
precharged automatically.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
10/28/05
5
