IS42/45SM/RM/VM16200D
1M
x
16Bits
x
2Banks Low Power Synchronous DRAM
Description
These IS42SM/RM/VM16200D are low power 33,554,432 bits CMOS Synchronous DRAM organized as 2 banks of 1,048,576 words x 16
bits. These products are offering fully synchronous operation and are referenced to a positive edge of the clock. All inputs and outputs
are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve high bandwidth. All input
and output voltage levels are compatible with LVCMOS.
Features
JEDEC standard 3.3V, 2.5V, 1.8V power supply
• Auto refresh and self refresh
• All pins are compatible with LVCMOS interface
• 4K refresh cycle / 64ms
• Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full Page for Sequential Burst
- 4 or 8 for Interleave Burst
• Programmable CAS Latency : 2,3 clocks
• All inputs and outputs referenced to the positive edge of the
system clock
• Data mask function by DQM
• Internal dual banks operation
• Burst Read Single Write operation
• Special Function Support
- PASR(Partial Array Self Refresh)
- Auto TCSR(Temperature Compensated Self Refresh)
- Programmable Driver Strength Control
- Full Strength or 1/2, 1/4, of Full Strength
- Deep Power Down Mode
• Automatic precharge, includes CONCURRENT Auto Precharge
Mode and controlled Precharge
Copyright © 2015 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its
products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services
described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information
and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or
effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to
its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Rev. A | November 2015
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IS42/45SM/RM/VM16200D
Figure1: 54Ball FBGA Ball Assignment
1
A
B
C
D
E
F
G
H
J
VSS
DQ14
DQ12
DQ10
DQ8
UDQM
NC
A8
VSS
2
DQ15
DQ13
DQ11
DQ9
NC
CLK
NC
A7
A5
3
VSSQ
VDDQ
VSSQ
VDDQ
VSS
CKE
A9
A6
A4
4
5
6
7
VDDQ
VSSQ
VDDQ
VSSQ
VDD
/CAS
BA
A0
A3
8
DQ0
DQ2
DQ4
DQ6
LDQM
/RAS
NC
A1
A2
9
VDD
DQ1
DQ3
DQ5
DQ7
/WE
/CS
A10
VDD
[Top View]
Rev. A | November 2015
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IS42/45SM/RM/VM16200D
Table2: Pin Descriptions
Pin
CLK
Pin Name
System Clock
Descriptions
The system clock input. All other inputs are registered to the
SDRAM on the rising edge CLK.
Controls internal clock signal and when deactivated, the SDRAM
will be one of the states among power down, suspend or self
refresh.
Enable or disable all inputs except CLK, CKE and DQM.
Selects bank to be activated during RAS activity.
Selects bank to be read/written during CAS activity.
Row Address
Column Address
Auto Precharge
: RA0~RA10
: CA0~CA8
: A10
CKE
/CS
BA
Clock Enable
Chip Select
Bank Address
A0~A10
Address
Row Address Strobe,
Column Address Strobe,
Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
No Connection
/RAS, /CAS, /WE
RAS, CAS and WE define the operation.
Refer function truth table for details.
Controls output buffers in read mode and masks input data in
write mode.
Data input/output pin.
Power supply for internal circuits and input buffers.
Power supply for output buffers.
No connection.
LDQM,UDQM
DQ0~DQ15
VDD/VSS
VDDQ/VSSQ
NC
Rev. A | November 2015
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IS42/45SM/RM/VM16200D
Figure2: Functional Block Diagram
CLK
CKE
EXTENDED
MODE
REGISTER
CLOCK
GENERATOR
TCSR
PASR
ADDRESS
ROW
ADDRESS
BUFFER &
REFRESH
COUNTER
BANK B
BANK A
ROW DECODER
ROW DECODER
MODE
REGISTER
SENSE AMPLIFIER
/CS
/RAS
/CAS
/WE
COLUMN
ADDRESS
BUFFER &
BURST
COUNTER
COLUMN DECODER
& LATCH CIRCUIT
Rev. A | November 2015
COMMAND DECODER
CONTROL LOGIC
DATA CONTROL CIRCUIT
DQM
LATCH CIRCUIT
INPUT & OUTPUT
BUFFER
DQ
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IS42/45SM/RM/VM16200D
Figure3: Simplified State Diagram
EXTENDED
MODE
REGISTER
SET
SELF
REFRESH
MODE
REGISTER
SET
MRS
IDLE
REF
CBR
REFRESH
ACT
DEEP
POWER
DOWN
POWER
DOWN
ROW
ACTIVE
CKE
CKE
ACTIVE
POWER
DOWN
WRITE
READ
PRE
WRITE
SUSPEND
CKE
WRITE
CKE
READ
READ
WRITE
CKE
CKE
READ
SUSPEND
WRITE A
SUSPEND
CKE
WRITE A
CKE
READ A
CKE
CKE
READ A
SUSPEND
POWER
ON
PRECHARGE
PRE-
CHARGE
Automatic Sequence
Manual Input
Rev. A | November 2015
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