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IS43R16400B

4Mx16

64Mb DDR SDRAM

FEATURES

•

VDD and VDDQ: 2.5V ± 0.2V (-5, -6)

VDD and VDDQ: 2.6V ± 0.1V (-4)

SSTL_2 compatible I/O

Double-data rate architecture; two data transfers

per clock cycle

Bidirectional, data strobe (DQS) is transmitted/

received with data, to be used in capturing data

at the receiver

DQS is edge-aligned with data for READs and

centre-aligned with data for WRITEs

Differential clock inputs (CK and CK)

DLL aligns DQ and DQS transitions with CK

transitions

Commands entered on each positive CK edge;

data and data mask referenced to both edges of

DQS

Four internal banks for concurrent operation

Data Mask for write data. DM masks write data

at both rising and falling edges of data strobe

Burst Length: 2, 4 and 8

Burst Type: Sequential and Interleave mode

Programmable CAS latency: 2, 2.5, 3 and 4

Auto Refresh and Self Refresh Modes

Auto Precharge

TRAS Lockout supported (tRAP = tRCD)

Configuration(s):

4M x16

Package:

66-pin TSOP-II

Lead-free package available

Temperature Range:

Commercial (0°C to +70°C)

Industrial (-40°C to +85°C)

OCTOBER 2012

DEVICE OVERVIEW

ISSI’s 64-Mbit DDR SDRAM achieves high speed data

transfer using pipeline architecture and two data word

accesses per clock cycle. The 67,108,864-bit memory

array is internally organized as four banks of 16Mb to

allow concurrent operations. The pipeline allows Read

and Write burst accesses to be virtually continuous, with

the option to concatenate or truncate the bursts. The

programmable features of burst length, burst sequence

and CAS latency enable further advantages. The

device is available in 16-bit data word size Input data is

registered on the I/O pins on both edges of Data Strobe

signal(s), while output data is referenced to both edges

of Data Strobe and both edges of CLK. Commands are

registered on the positive edges of CLK.

An Auto Refresh mode is provided, along with a Self

Refresh mode. All I/Os are SSTL_2 compatible.

•

ADDRESS TABLE

Parameter

Configuration

Bank Address

Pins

Autoprecharge

Pins

Row Addresses

Column Address

Refresh Count

4M x 16

1M x 16 x 4 banks

BA0, BA1

A10/AP

A0 – A11

A0 – A7

4K / 64ms

OPTIONS

KEY TIMING PARAMETERS

Speed Grade

Max CL = 4

Max CL = 3

Max CL = 2.5

Max CL = 2

-4

250

200

—

-5

—

200

166

133

-6

—

166

133

Units

MHz

notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-

est version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-

ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications

unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Integrated Silicon Solution, Inc.

Rev.B

10/22/2011

IS43R16400B

FUNCTIONAL BLOCK DIAGRAM (4Mx16)

CLK

CKE

RAS

CAS

COMMAND

DECODER

CLOCK

GENERATOR

MODE REGISTER

AND EXTENDED

MODE REGISTER

DATA IN

BUFFER

LDM, UDM

REFRESH

CONTROLLER

UDQS, LDQS

I/O 0-15

SELF

A11

A10

BA0

BA1

REFRESH

CONTROLLER

DATA OUT

BUFFER

DDQ

REFRESH

COUNTER

4096

ROW DECODER

MULTIPLEXER

MEMORY CELL

ARRAY

ROW

ADDRESS

LATCH

ROW

ADDRESS

BUFFER

BANK 0

SENSE AMP I/O GATE

COLUMN

ADDRESS LATCH

512

(x16)

BANK CONTROL LOGIC

BURST COUNTER

COLUMN

ADDRESS BUFFER

COLUMN DECODER

Integrated Silicon Solution, Inc.

Rev.B

10/22/2011

IS43R16400B

PIN CONFIGURATIONS

66 pin TSOP - Type II for x16

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DDQ

LDQS

VDD

LDM

CAS

RAS

BA0

BA1

A10/AP

VDD

DQ15

DQ14

DQ13

DQ12

DQ11

DQ10

DQ9

DQ8

SSQ

UDQS

VREF

VSS

UDM

CKE

A11

VSS

PIN DESCRIPTION:

A0-A11

A0-A7

BA0, BA1

DQ0 – DQ15

CK, CK

CKE

CAS

RAS

Row Address Input

Column Address Input

Bank Select Address

Data I/O

System Clock Input

Clock Enable

Chip Select

Column Address Strobe

Command

Row Address Strobe

Command

LDM, UDM

LDQS, UDQS

VDD

VDDQ

VSS

VSSQ

VREF

Write Enable

Data Write Mask

Data Strobe

Power

Power Supply for I/O Pins

Ground

Ground for I/O Pins

SSTL_2 reference voltage

No Connection

Integrated Silicon Solution, Inc.

Rev.B

10/22/2011

IS43R16400B

PIN FUNCTIONAL DESCRIPTIONS

Symbol

CK, CK

Type

Input

Description

Clock: CK and CK are differential clock inputs. All address and control input signals are sampled

on the crossing of the positive edge of CK and negative edge of CK. Input and output data is

referenced to the crossing of CK and CK (both directions of crossing). Internal clock signals are

derived from CK/ CK.

Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and

device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-

DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWERDOWN (row

ACTIVE in any bank). CKE is synchronous for all functions except for SELF REFRESH EXIT,

which is achieved asynchronously. Input buffers, excluding CK, CK and CKE, are disabled during

power-down and self refresh mode which are contrived for low standby power consumption.

Chip Select: CS enables (registered LOW) and disables (registered HIGH) the command

decoder. All commands are masked when CS is registered HIGH. CS provides for external bank

selection on systems with multiple banks. CS is considered part of the command code.

Input Command Inputs:

RAS, CAS

and

WE (along with CS)

define the command being

entered.

Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is

sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges

of DQS. Although DM pins are input-only, the DM loading matches the DQ and DQS loading.

LDM corresponds to the data on DQ0-DQ7, UDM corresponds to the data on DQ8-DQ15.

BA0, BA1

A [11:0]

Input

Input Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or

PRECHARGE command is being applied.

Address Inputs: provide the row address for ACTIVE commands, and the column address

and AUTO PRECHARGE bit for READ / WRITE commands, to select one location out of the

memory array in the respective bank. The address inputs also provide the opcode during a

MODE REGISTER SET command.

Data Bus: Input / Output

Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered

with write data. Used to capture write data.

LDQS corresponds to the data on DQ0-DQ7, UDQS corresponds to the data on DQ8-DQ15.

VREF

VDDQ

VSSQ

VDD

VSS

Supply

No Connect: Should be left unconnected.

SSTL_2 reference voltage

I/O Power Supply

I/O Ground

Power Supply

Ground

CKE

Input

RAS, CAS,

DM:

LDM, UDM

Input

DQ:

DQ0-DQ15

DQS:

LDQS,UDDS

I/O

Integrated Silicon Solution, Inc.

Rev.B

10/22/2011

IS43R16400B

SIMPLIFIED STATE DIAGRAM

Power

Applied

Power

Precharge

PREALL

REFS

REFSX

MRS

EMRS

MRS

REFA

Auto

Refresh

Self

Refresh

Idle

CKEH

CKEL

Active

Power

Down

ACT

Precharge

Power

Down

CKEH

CKEL

Write

Write A

Write

Row

Active

Burst Stop

Read

Read A

Read

Write A

Read

PRE

Read A

Write

PRE

Read

PRE

Precharge

PREALL

Automatic Sequence

Command Sequence

PREALL = Precharge All Banks

CKEL = Enter Power Down

MRS = Mode Register Set

CKEH = Exit Power Down

EMRS = Extended Mode Register Set

ACT = Active

Integrated Silicon Solution, Inc.

Rev.B

10/22/2011

REFS = Enter Self Refresh

Write A = Write with Autoprecharge

REFSX = Exit Self Refresh

Read A = Read with Autoprecharge

REFA = Auto Refresh

PRE = Precharge