without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
07/11/05
1
IS43R16800A
FUNCTIONAL BLOCK DIAGRAM (
X
16)
CLK
CLK
CKE
CS
RAS
CAS
WE
COMMAND
DECODER
&
CLOCK
GENERATOR
MODE
REGISTER
REFRESH
CONTROLLER
ISSI
LDM, UDM
DATA IN
BUFFER
16
16
2
2
®
I/O 0-15
UDQS, LDQS
SELF
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA0
BA1
14
REFRESH
CONTROLLER
DATA OUT
BUFFER
16
16
V
DD
/V
DDQ
V
ss
/V
ss
Q
REFRESH
COUNTER
2
4096
4096
4096
4096
12
ROW DECODER
MULTIPLEXER
MEMORY CELL
ARRAY
12
14
ROW
ADDRESS
LATCH
12
12
ROW
ADDRESS
BUFFER
BANK 0
SENSE AMP I/O GATE
COLUMN
ADDRESS LATCH
9
512
(x16)
BANK CONTROL LOGIC
BURST COUNTER
COLUMN DECODER
COLUMN
ADDRESS BUFFER
9
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
07/11/05
IS43R16800A
PIN CONFIGURATIONS
66 pin TSOP - Type II for x16
V
DD
DQ0
V
DD
Q
DQ1
DQ2
V
SS
Q
DQ3
DQ4
V
DD
Q
DQ5
DQ6
V
SS
Q
DQ7
NC
V
DDQ
LDQS
NC
VDD
NC
LDM
WE
CAS
RAS
CS
NC
BA0
BA1
A10
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
V
SS
DQ15
V
SS
Q
DQ14
DQ13
V
DD
Q
DQ12
DQ11
V
SS
Q
DQ10
DQ9
V
DD
Q
DQ8
NC
V
SSQ
UDQS
NC
VREF
VSS
UDM
CLK
CLK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
VSS
ISSI
®
PIN DESCRIPTIONS
A0-A11
A0-A8
BA0, BA1
DQ0 to DQ15
CLK
CKE
CS
RAS
CAS
Row Address Input
Column Address Input
Bank Select Address
Data I/O
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
Column Address Strobe Command
WE
LDM, UDM
LDQS, UDQS
V
DD
Vss
V
DDQ
Vss
Q
NC
Write Enable
x16 Input/Output Mask
Data Strobe
Power
Ground
Power Supply for I/O Pin
Ground for I/O Pin
No Connection
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
07/11/05
3
IS43R16800A
PIN FUNCTIONS
Symbol
A0-A11
Type
Input Pin
ISSI
®
BA0, BA1
Input Pin
CAS
CKE
Input Pin
Input Pin
CLK,
CLK
Input Pin
CS
Input Pin
LDM, UDM
Input Pin
LDQS, UDQS
Input/Output Pin
DQ0-DQ15
Input/Output Pin
NC
RAS
WE
VDDQ
VDD
VREF
VSSQ
VSS
4
—
Input Pin
Input Pin
Power
Power
Power
Power
Power
Supply
Supply
Supply
Supply
Supply
Pin
Pin
Pin
Pin
Pin
Function (In Detail)
Address inputs are sampled during several commands. During an Active
command, A0-A11 select a row to open. During a Read or Write command,
A0-A8 select a starting column for a burst. During a Pre-charge command,
A10 determines whether all banks are to be pre-charged, or a single bank.
During a Load Mode Register command, the address inputs select an
operating mode.
Bank Address inputs are used to select a bank during Active, Pre-charge,
Read, or Write commands. During a Load Mode Register command, BA0
and BA1 are used to select between the Base or Extended Mode Register
CAS
is Column Access Strobe, which is an input to the device command
along with
RAS
and
WE.
See “Command Truth Table” for details.
Clock Enable: CKE High activates and CKE Low de-activates internal clock
signals and input/output buffers. When CKE goes Low, it can allow Self
Refresh, Pre-charge Power Down, and Active Power Down. CKE must be
High during entire Read and Write accesses. Input buffers except CLK,
CLK,
and CKE are disabled during Power Down. CKE uses an SSTL 2
input, but will detect a LVCMOS Low level after VDD is applied.
All address and command inputs are sampled on the rising edge of the
clock input CLK and the falling edge of the differential clock input
CLK.
Output data is referenced from the crossings of CLK and
CLK.
The Chip Select input enables the Command Decoding block of the device.
When
CS
is disabled, a NOP occurs. See “Command Truth Table” for
details. Multiple DDR SDRAM devices can be managed with
CS.
These are the Data Mask inputs. During a Write operation, the Data Mask
input allows masking of the data bus. DM is sampled on each edge of DQS.
There are two Data Mask input pins for the x16 DDR SDRAM. Each input
applies to DQ0-DQ7, or DQ8-DQ15.
These are the Data Strobe inputs. The Data Strobe is used for data capture.
During a Read operation, the DQS output signal from the device is edge-
aligned with valid data on the data bus. During a Write operation, the DQS
input should be issued to the DDR SDRAM device when the input values on
DQ inputs are stable. There are two Data Strobe pins for the x16 DDR
SDRAM. Each of the two Data Strobe pins applies to DQ0-DQ7, or DQ8-
DQ15.
The pins DQ0 to DQ15 represent the data bus. For Write operations, the
data bus is sampled on Data Strobe. For Read operations, the data bus is
sampled on the crossings of CK and
CK.
No Connect: This pin should be left floating. These pins could be used for
256Mbit or higher density DDR SDRAM.
RAS
is Row Access Strobe, which is an input to the device command
along with
CAS
and
WE.
See “Command Truth Table” for details.
WE
is Write Enable, which is an input to the device command along with
RAS
and
CAS.
See “Command Truth Table” for details.
VDDQ is the output buffer power supply.
VDD is the device power supply.
VREF is the reference voltage for SSTL 2.
VSSQ is the output buffer ground.
VSS is the device ground.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
07/11/05
IS43R16800A
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
DD MAX
V
DDQ MAX
V
IN
, V
REF
P
D MAX
I
CS
T
OPR
T
STG
Parameters
Maximum Supply Voltage
Maximum Supply Voltage for Output Buffer
Input Voltage, Reference Voltage
Allowable Power Dissipation
Output Shorted Current
Operating Temperature
Com.
Storage Temperature
Rating
–1.0 to +3.6
–1.0 to +3.6
–1.0 to +3.6
1
50
0 to +70
–55 to +125
Unit
V
V
V
W
mA
°C
°C
ISSI
®
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
2. All voltages are referenced to Vss.
RECOMMENDED DC OPERATING CONDITIONS (SSTL_2 Input/Output, T
A
= 0
o
C to +70
o
C)
Symbol
V
DD
V
DDQ
(1)
V
TT
V
IH
(2)
V
IL
(3)
V
REF
V
IN
(DC)
(4)
V
IX
(DC)
V
ID
(DC)
(5,6)
I
IL
I
OL
V
OH
V
OL
Parameter
Supply Voltage
I/O Supply Voltage
I/O Termination Voltage
Input High Voltage
Input Low Voltage
I/O Reference Voltage
Input Voltage Level for
CLK and
CLK
Crossing Point Voltage
Level for CLK and
CLK
Input Differential Voltage
Level for CLK and
CLK
Input Leakage Current
Output Leakage Current
Output High Voltage
Level
Output Low Voltage
Level
Test Condition
Min
2.5
2.5
V
REF
- 0.04
V
REF
+ 0.15
V
SSQ
- 0.3
0.49 x V
DDQ
-0.3
0.5 x V
DDQ
- 0.2
0.36
0
≤
V
IN
≤
V
DD
, with all inputs
at V
SS
, except tested input
Output disabled;
0V
≤
V
OUT
≤
V
DDQ
I
OH
= -15.2mA
I
OL
= +15.2mA
-2
-5
V
TT
+ 0.76
—
Typ.
2.6
2.6
V
REF
—
—
0.5 x V
DDQ
—
Max
2.7
2.7
V
REF
+ 0.04
V
DDQ
+ 0.3
V
DDQ
- 0.15
0.51 x V
DDQ
V
DDQ
+ 0.3
Unit
V
V
V
V
V
V
V
V
V
µA
µA
V
V
0.5 x V
DDQ
0.5 x V
DDQ
+ 0.2
—
—
—
—
—
V
DDQ
+ 0.6
2
5
—
V
REF
- 0.76
Note:
1. V
DDQ
must always be less than or equal to V
DD
.
2. V
IH
is allowed to exceed V
DD
up to 3.6V for the period shorter than or equal to 5ns.
3. V
IL
is allowed to drop to -1.0V for the period shorter than or equal to 5ns.
4. V
IN
(DC) specifies the allowable DC execution of each differential input.
5. V
ID
(DC) specifies the input differential voltage required for switching.
6. V
IH
for CLK or
CLK
> V
REF
+ 0.18V; V
IL
for CLK or
CLK
< V
REF
- 0.18V.
Integrated Silicon Solution, Inc. — 1-800-379-4774
