1Gb: x18, x36 RLDRAM 3
Features
RLDRAM 3
Features
IS49RL18640-4 Meg x 18 x 16 Banks
IS49RL36320–2 Meg x 36 x 16 Banks
Options
• Clock cycle and
t
RC timing
•
1200
MHz DDR operation (2400 Mb/s/ball
data rate)
• Organization
–
64 Meg x 18, and 32 Meg x 36 common I/O (CIO)
–
16 banks
• 1.2V center-terminated push/pull I/O
•
2.5V V
EXT
, 1.35V V
DD
, 1.2V V
DDQ
(optional 1.35V V
DDQ
for 2400 operation only).
•
• SDR addressing
• Programmable READ/WRITE latency (RL/WL) and
burst length
• Data mask for WRITE commands
•
• Fr
x,
DK
x#)
and output data clocks (QK
x,
QK
x#)
• On-die DLL generates CK edge-aligned data and
•
•
•
•
•
•
64ms refresh (128K refresh per 64ms)
168-ball FBGA package
40 Ω or 60 Ω matched
impedance outputs
Integrated on-die termination (ODT)
Single or multibank writes
Extended operating range (200–1200 MHz)
Reduced
cycle time (
t
RC (MIN) = 6.67 - 8ns)
–
0.83
ns and
t
RC (MIN) =
6.67ns
(RL3-2400)
for -083F
–
0.83
ns and
t
RC (MIN) =
7.5ns
(RL3-2400)
for -083E
–
0.93
ns and
t
RC (MIN) =
7.5ns
(RL3-2133)
for -093F
–
0.93
ns and
t
RC (MIN) =
8ns
(RL3-2133)
for -093E
– 1.07ns and
t
RC (MIN) =
8ns
(RL3-1866)
for -107E
•
- 64 Meg x 18
- 32 Meg x 36
Operating Temperature
– Commercial (T
C
= 0° to +95°C)
– Industrial (T
C
= –40°C to +95°C)
Package
– 168-ball FBGA (Pb-free)
•
•
• READ training register
• Multiplexed and non-multiplexed addressing capa-
bilities
• Mirror function
• Output driver and ODT calibration
•
Post Package Repar - 1 row per half bank
• JTAG interface (IEEE 1149.1-2001)
Copyright © 2019 Integrated Silicon Solu on, Inc. All rights reserved. ISSI reserves the right to make changes to this specifica on and its products at any me without
no ce. ISSI assumes no liability arising out of the applica on or use of any informa on, products or services described herein. Customers are advised to obtain the
latest version of this device specifica on before relying on any published informa on and before placing orders for prodsu.c t
Integrated Silicon Solu on, Inc. does not recommend the use of any of its products in life support applica ons where the failure or malfunc on of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effec veness. Products are not authorized for use in such
applica ons unless Integrated Silicon Solu on, Inc. receives wri en assurance to its sa sfac on, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) poten al liability of Integrated Silicon Solu on, Inc is adequately protected under the circumstances
RLDRAM® is a registered trademark of Micron Technology, Inc.
www.issi.com
Rev.00C
09/18/2019
1
1Gb: x18, x36 RLDRAM 3
Features
Figure 1: 1Gb RLDRAM
®
3 Part Numbers
Example Part Number: IS49RL18640-083EBLI
-
IS49RL
Speed Package Temp
Temperature
64 Meg x 18
32 Meg x 36
Speed Grade
-083F
-083E
-093F
-093E
-107E
t
CK
t
CK
t
CK
t
CK
t
CK
18640
36320
Commercial
Industrial
None
I
Package
168-ball BGA (Pb-free)
= 0.83ns (6.67ns
t
RC)
= 0.83ns (7.5ns
t
RC)
= 0.93ns (7.5ns
t
RC)
= 0.93ns (8ns
t
RC)
= 1.07ns (8ns
t
RC)
BL
www.issi.com
Rev.00C
09/18/2019
2
1Gb
: x18, x36 RLDRAM 3
Contents
Contents
General Description .........................................................................................................................................
9
General Notes ..............................................................................................................................................
9
State Diagram ................................................................................................................................................
10
Functional Block Diagrams ............................................................................................................................. 11
Ball Assignments and Descriptions ................................................................................................................. 13
Electrical Characteristics – I
DD
Specifications .................................................................................................. 17
Electrical Specifications – Absolute Ratings and I/O Capacitance .....................................................................
20
Absolute Maximum Ratings ........................................................................................................................
20
Input/Output Capacitance ..........................................................................................................................
21
AC and DC Operating Conditions .................................................................................................................... 22
AC Overshoot/Undershoot Specifications .................................................................................................... 23
Slew Rate Definitions for Single-Ended Input Signals ................................................................................... 27
Slew Rate Definitions for Differential Input Signals ...................................................................................... 29
ODT Characteristics .......................................................................................................................................
30
ODT Resistors ............................................................................................................................................
30
ODT Sensitivity ..........................................................................................................................................
32
Output Driver Impedance ...............................................................................................................................
33
Output Driver Sensitivity ............................................................................................................................
35
Output Characteristics and Operating Conditions ............................................................................................
36
Reference Output Load ...............................................................................................................................
39
Slew Rate Definitions for Single-Ended Output Signals .....................................................................................
40
Slew Rate Definitions for Differential Output Signals ........................................................................................
41
Speed Bin Tables ............................................................................................................................................
42
AC Electrical Characteristics ...........................................................................................................................
43
Temperature and Thermal Impedance Characteristics .....................................................................................
49
Command and Address Setup, Hold, and Derating ...........................................................................................
51
Data Setup, Hold, and Derating .......................................................................................................................
58
Commands ....................................................................................................................................................
65
MODE REGISTER SET (MRS) Command .........................................................................................................
66
Mode Register 0 (MR0) ....................................................................................................................................
67
t
RC .............................................................................................................................................................
68
Data Latency ..............................................................................................................................................
68
DLL Enable/Disable ...................................................................................................................................
68
Address Multiplexing ..................................................................................................................................
69
Mode Register 1 (MR1) ....................................................................................................................................
70
Output Drive Impedance ............................................................................................................................
70
DQ On-Die Termination (ODT) ...................................................................................................................
71
DLL Reset ...................................................................................................................................................
71
ZQ Calibration ............................................................................................................................................
71
ZQ Calibration Long ...................................................................................................................................
72
ZQ Calibration Short ...................................................................................................................................
72
AUTO REFRESH Protocol ............................................................................................................................
73
Burst Length (BL) .......................................................................................................................................
73
Mode Register 2 (MR2) ....................................................................................................................................
73
READ Training Register (RTR) .....................................................................................................................
75
WRITE Protocol ..........................................................................................................................................
76
WRITE Command ..........................................................................................................................................
76
Multibank WRITE .......................................................................................................................................
76
Post Package Repair – PPR .............................................................................................................................. 79
PPR Row Repair Sequence .......................................................................................................................... 79
READ Command ............................................................................................................................................
81
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Rev.00C
09/18/2019
3
1Gb: x18, x36 RLDRAM 3
Contents
............................................................................................................................
AUTO REFRESH Command
............................................................................................................................
INITIALIZATION Operation
WRITE Operation ...............................................................................................................................................
READ Operation .................................................................................................................................................
..............................................................................................................................
AUTO REFRESH Operation
RESET Operation .................................................................................................................................................
Mirror Function ...................................................................................................................................................
81
84
87
91
94
97
99
Multiplexed Address Mode ...............................................................................................................................
100
........................................................................................... 105
Data Latency in Multiplexed Address Mode
............................................................................ 105
REFRESH Command in Multiplexed Address Mode
....................................................................................................
IEEE 1149.1 Serial Boundary Scan (JTAG)
Disabling the JTAG Feature .........................................................................................................................
Test Access Port (TAP) ..................................................................................................................................
TAP Controller ...............................................................................................................................................
Performing a TAP RESET ..............................................................................................................................
TAP Registers ..................................................................................................................................................
TAP Instruction Set ........................................................................................................................................
109
109
109
110
112
112
113
Ordering Information
............................................................................................................ ..121
Package Dimensions ........................................................................................................... 122
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Rev.00C
09/18/2019
4
1Gb:
x18, x36 RLDRAM 3
Figures
List of Figures
Figure 1:
Figure 2:
Figure 3:
Figure
4:
1Gb
RLDRAM
®
3 Part Numbers .............................................................................. ....................... 2
Simplified State Diagram ..................................................................................................................10
64
Meg x 18 Functional Block Diagram ............................................................................................. 11
32
Meg x 36 Functional Block Diagram ............................................................................................. 13
Figure
5:
Single-Ended Input Signal ............................................................................................................... 22
Figure
6:
Overshoot ....................................................................................................................................... 23
Figure
7:
Undershoot .................................................................................................................................... 23
Figure
8:
V
IX
for Differential Signals ................................................................................................................ 24
Figure
9:
Single-Ended Requirements for Differential Signals ........................................................................ 25
Figure
10:
Definition of Differential AC Swing and
t
DVAC ................................................................................26
Figure
11:
Nominal Slew Rate Definition for Single-Ended Input Signals .......................................................... 27
Figure 12: Nominal Slew Rate Definition for Single-Ended Input Signals .......................................................... 27
Figure 13: Nominal Differential Input Slew Rate Definition for CK, CK#, DKx, and DKx# .................................. 28
Figure 14: ODT Levels and I-V Characteristics ................................................................................................
29
Figure 15: Output Driver ................................................................................................................................
3
2
Figure 16: DQ Output Signal ..........................................................................................................................
37
Figure 17: Differential Output Signal ..............................................................................................................
38
Figure 18: Reference Output Load for AC Timing and Output Slew Rate ...........................................................
38
Figure 19: Nominal Slew Rate Definition for Single-Ended Output Signals .......................................................
39
Figure 20: Nominal Differential Output Slew Rate Definition for QKx, QKx# .....................................................
40
Figure 21: Example Temperature Test Point Location ......................................................................................
49
Figure 22: Nominal Slew Rate and
t
VAC for
t
IS (Command and Address - Clock) ...............................................
53
Figure 23: Nominal Slew Rate for
t
IH (Command and Address - Clock) ............................................................
54
Figure 24: Tangent Line for
t
IS (Command and Address - Clock) ......................................................................
55
Figure 25: Tangent Line for
t
IH (Command and Address - Clock) .....................................................................
56
Figure 26: Nominal Slew Rate and
t
VAC for
t
DS (DQ - Strobe) ..........................................................................
60
Figure 27: Nominal Slew Rate for
t
DH (DQ - Strobe) ........................................................................................
61
Figure 28: Tangent Line for
t
DS (DQ - Strobe) .................................................................................................
62
Figure 29: Tangent Line for
t
DH (DQ - Strobe) ................................................................................................
63
Figure 30: MRS Command Protocol ...............................................................................................................
65
Figure 31: MR0 Definition for Non-Multiplexed Address Mode ........................................................................
66
Figure 32: MR1 Definition for Non-Multiplexed Address Mode ........................................................................
69
Figure 33: ZQ Calibration Timing (ZQCL and ZQCS) .......................................................................................
71
Figure 34: Read Burst Lengths ........................................................................................................................
73
Figure 35: MR2 Definition for Non-Multiplexed Address Mode ........................................................................
74
Figure 36: READ Training Function - Back-to-Back Readout ............................................................................
76
Figure
37:
WRITE Command .........................................................................................................................
77
Figure
38:
Entry, Repair, and Exit Timing Diagram ........................................................................................
80
Figure 39:
Figure
40:
Figure 41:
Figure 42:
Figure 43:
Figure 44:
Figure 45:
Figure 46:
Figure 47:
Figure 48:
Figure 49:
Figure
50:
Figure 51:
READ Command ...........................................................................................................................
Bank Address-Controlled AUTO REFRESH Command .....................................................................
Multibank AUTO REFRESH Command ...........................................................................................
Power-Up/Initialization Sequence ...............................................................................................
WRITE Burst .................................................................................................................................
Consecutive WRITE Bursts .............................................................................................................
WRITE-to-READ ............................................................................................................................
WRITE - DM Operation ..................................................................................................................
Consecutive Quad Bank WRITE Bursts ...........................................................................................
Interleaved READ and Quad Bank WRITE Bursts .............................................................................
Basic READ Burst ..........................................................................................................................
Consecutive READ Bursts (BL = 2) ..................................................................................................
Consecutive READ Bursts (BL = 4) ..................................................................................................
5
81
82
83
85
87
88
88
89
90
90
91
92
92
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Rev.00C
09/18/2019
stm32/stm8
