IS61C256AH
32K x 8 HIGH-SPEED CMOS STATIC RAM
FEATURES
• High-speed access time: 10, 12, 15, 20, 25 ns
• Low active power: 400 mW (typical)
• Low standby power
— 250
µW
(typical) CMOS standby
— 55 mW (typical) TTL standby
• Fully static operation: no clock or refresh
required
• TTL compatible inputs and outputs
• Single 5V power supply
ISSI
®
MAY 1999
DESCRIPTION
The
ISSI
IS61C256AH is a very high-speed, low power,
32,768 word by 8-bit static RAMs. They are fabricated using
ISSI
's high-performance CMOS technology. This highly reli-
able process coupled with innovative circuit design tech-
niques, yields access times as fast as 10 ns maximum.
When
CE
is HIGH (deselected), the device assumes a standby
mode at which the power dissipation can be reduced down to
250
µW
(typical) with CMOS input levels.
Easy memory expansion is provided by using an active LOW
Chip Enable (
CE
) input and an active LOW Output Enable (
OE
)
input. The active LOW Write Enable (
WE
) controls both writing
and reading of the memory.
The IS61C256AH is pin compatible with other 32K x 8 SRAMs
and are available in 28-pin PDIP, SOJ, and TSOP (Type I)
packages.
FUNCTIONAL BLOCK DIAGRAM
A0-A14
DECODER
32K X 8
MEMORY ARRAY
VCC
GND
I/O
DATA
CIRCUIT
I/O0-I/O7
COLUMN I/O
CE
OE
WE
CONTROL
CIRCUIT
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which
may appear in this publication. © Copyright 1999, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
SR020-1O
05/24/99
1
IS61C256AH
PIN CONFIGURATION
28-Pin DIP and SOJ
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
ISSI
PIN CONFIGURATION
28-Pin TSOP
OE
A11
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
9
8
®
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
PIN DESCRIPTIONS
A0-A14
Address Inputs
Chip Enable Input
Output Enable Input
Write Enable Input
Bidirectional Ports
Power
Ground
TRUTH TABLE
Mode
CE
OE
WE
I/O0-I/O7
Vcc
GND
WE
CE OE
H
L
L
L
X
H
L
X
I/O Operation Vcc Current
High-Z
High-Z
D
OUT
D
IN
I
SB
1
, I
SB
2
I
CC
I
CC
I
CC
Not Selected
X
(Power-down)
Output Disabled H
Read
H
Write
L
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
T
BIAS
T
STG
P
T
I
OUT
Parameter
Terminal Voltage with Respect to GND
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current (LOW)
Value
–0.5 to +7.0
–55 to +125
–65 to +150
1.5
20
Unit
V
°C
°C
W
mA
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
SR020-1O
05/24/99
IS61C256AH
OPERATING RANGE
Range
Ambient Temperature
Commercial
0°C to +70°C
Industrial
–40°C to +85°C
Speed
-10, -12
-15, -20, -25
-12
-15, -20, -25
V
CC
5V
±
5%
5V
±
10%
5V
±
5%
5V
±
10%
ISSI
®
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
Symbol Parameter
V
OH
V
OL
V
IH
V
IL
I
LI
I
LO
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
(1)
Input Leakage
Output Leakage
GND
≤
V
IN
≤
V
CC
GND
≤
V
OUT
≤
V
CC
,
Outputs Disabled
Com.
Ind.
Com.
Ind.
Test Conditions
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
Min.
2.4
—
2.2
–0.5
–5
–10
–5
–10
Max.
—
0.4
V
CC
+ 0.5
0.8
5
10
5
10
Unit
V
V
V
V
µA
µA
Note:
1. V
IL
= –3.0V for pulse width less than 10 ns.
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
Symbol
I
CC
I
SB
1
Parameter
Vcc Dynamic Operating
Supply Current
TTL Standby Current
(TTL Inputs)
CMOS Standby
Current (CMOS Inputs)
Test Conditions
V
CC
= Max.,
CE
= V
IL
I
OUT
= 0 mA, f = f
MAX
V
CC
= Max.,
V
IN
= V
IH
or V
IL
CE
≥
V
IH
, f = 0
V
CC
= Max.,
CE
≥
V
CC
– 0.2V,
V
IN
≥
V
CC
– 0.2V, or
V
IN
≤
0.2V, f = 0
Com.
Ind.
Com.
Ind.
Com.
Ind.
-10
-12
-15
-20
-25
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
—
—
—
—
—
—
165
—
25
—
2
—
—
—
—
—
—
—
155
165
25
30
2
10
—
—
—
—
—
—
145
155
25
30
2
10
—
—
—
—
—
—
135
145
25
30
2
10
—
—
—
—
—
—
125
135
25
30
2
10
mA
mA
I
SB
2
mA
Note:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
CAPACITANCE
(1,2)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
8
10
Unit
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25°C, f = 1 MHz, Vcc = 5.0V.
Integrated Silicon Solution, Inc. — 1-800-379-4774
SR020-1O
05/24/99
3
IS61C256AH
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
Symbol
Parameter
Read Cycle Time
Address Access Time
Output Hold Time
-10
Min. Max
10
—
2
—
—
0
—
2
—
0
—
—
10
—
10
5
—
5
—
5
—
10
-12
Min. Max.
12
—
2
—
—
0
—
3
—
0
—
—
12
—
12
5
—
6
—
7
—
12
-15
Min. Max.
15
—
2
—
—
0
—
3
—
0
—
—
15
—
15
7
—
7
—
8
—
15
-20
Min. Max.
20
—
2
—
—
0
—
3
—
0
—
—
20
—
20
8
—
9
—
9
—
18
-25
Min. Max.
25
—
2
—
—
0
—
3
—
0
—
—
25
—
25
9
—
10
—
10
—
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ISSI
®
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
(2)
t
HZOE
(2)
t
LZCE
(2)
t
HZCE
(2)
t
PU
(3)
t
PD
(3)
CE
Access Time
OE
Access Time
OE
to Low-Z Output
OE
to High-Z Output
CE
to Low-Z Output
CE
to High-Z Output
CE
to Power-Up
CE
to Power-Down
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of
0 to 3.0V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured
±500
mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Levels
Output Load
Unit
0V to 3.0V
3 ns
1.5V
See Figures 1 and 2
AC TEST LOADS
480
Ω
5V
5V
480
Ω
OUTPUT
30 pF
Including
jig and
scope
255
Ω
OUTPUT
5 pF
Including
jig and
scope
255
Ω
Figure 1
Figure 2
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
SR020-1O
05/24/99
IS61C256AH
AC WAVEFORMS
READ CYCLE NO. 1
(1,2)
t
RC
ADDRESS
ISSI
®
t
AA
t
OHA
D
OUT
PREVIOUS DATA VALID
t
OHA
DATA VALID
READ1.eps
READ CYCLE NO. 2
(1,3)
t
RC
ADDRESS
t
AA
OE
t
OHA
t
DOE
CE
t
HZOE
t
LZOE
t
ACE
t
LZCE
t
HZCE
DATA VALID
CE_RD2.eps
D
OUT
HIGH-Z
Notes:
1.
WE
is HIGH for a Read Cycle.
2. The device is continuously selected.
OE
,
CE
= V
IL
.
3. Address is valid prior to or coincident with
CE
LOW transitions.
Integrated Silicon Solution, Inc. — 1-800-379-4774
SR020-1O
05/24/99
5
