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IS61LF102418A-65B3

SRAM 18Mb,Flow-Through,Sync,1Mb x 18,6.5ns,3.3v or 2.5V I/O,165 Ball BGA

器件类别：存储   

厂商名称：ISSI(芯成半导体)

厂商官网：http://www.issi.com/

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器件参数
参数名称
属性值
Product Attribute
Attribute Value
制造商
Manufacturer
ISSI(芯成半导体)
产品种类
Product Category
SRAM
Memory Size
18 Mbit
Access Time
6.5 ns
Maximum Clock Frequency
133 MHz
电源电压-最大
Supply Voltage - Max
3.465 V
电源电压-最小
Supply Voltage - Min
3.135 V
Supply Current - Max
250 mA
最小工作温度
Minimum Operating Temperature
0 C
最大工作温度
Maximum Operating Temperature
+ 70 C
安装风格
Mounting Style
SMD/SMT
封装 / 箱体
Package / Case
BGA-165
数据速率
Data Rate
SDR
类型
Type
Synchronous
Number of Ports
2
工厂包装数量
Factory Pack Quantity
144
文档预览
IS61LF25672A IS61VF25672A
IS61LF51236A IS61VF51236A
IS61LF102418A IS61VF102418A
256K x 72, 512K x 36, 1024K x 18
18Mb SYNCHRONOUS FLOW-THROUGH
STATIC RAM
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Burst sequence control using MODE input
• Three chip enable option for simple depth expan-
sion and address pipelining
• Common data inputs and data outputs
• Auto Power-down during deselect
• Single cycle deselect
• Snooze MODE for reduced-power standby
• JTAG Boundary Scan for PBGA package
• Power Supply
LF: V
DD
3.3V + 5%, V
DDQ
3.3V/2.5V + 5%
VF: V
DD
2.5V + 5%, V
DDQ
2.5V + 5%
• JEDEC 100-Pin TQFP, 119-pin PBGA, 209-Ball
PBGA and 165-pin PBGA packages.
• Lead-free available
JULY 2010
DESCRIPTION
The
ISSI
IS61LF/VF25672A, IS61LF/VF51236A and
IS61LF/VF102418A are high-speed, low-power synchro-
nous static RAMs designed to provide burstable, high-
performance memory for communication and networking
applications. The IS61LF/VF25672A is organized as
262,144 words by 72 bits. The IS61LF/VF51236A is orga-
nized as 524,288 words by 36 bits. The IS61LF/VF102418A
is organized as 1,048,576 words by 18 bits. Fabricated
with
ISSI
's advanced CMOS technology, the device inte-
grates a 2-bit burst counter, high-speed SRAM core, and
high-drive capability outputs into a single monolithic cir-
cuit. All synchronous inputs pass through registers con-
trolled by a positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be one
to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
Byte write operation is performed by using byte write
enable (BWE) input combined with one or more individual
byte write signals (BWx). In addition, Global Write (GW) is
available for writing all bytes at one time, regardless of the
byte write controls.
Bursts can be initiated with either
ADSP
(Address Status
Processor) or
ADSC
(Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the
ADV
(burst address ad-
vance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH or
left floating.
FAST ACCESS TIME
Symbol
t
KQ
t
KC
Parameter
Clock Access Time
Cycle Time
Frequency
-6.5
6.5
7.5
133
-7.5
7.5
8.5
117
Units
ns
ns
MHz
Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.
Rev. K
07/29/2010
1
IS61LF25672A
IS61VF25672A
BLOCK DIAGRAM
IS61LF51236A IS61LF102418A
IS61VF51236A IS61VF102418A
MODE
Q0
A0'
CLK
CLK
A0
BINARY
COUNTER
ADV
ADSC
ADSP
CE
CLR
Q1
A1'
A1
256Kx72;
512Kx36;
1024Kx18;
MEMORY ARRAY
17/18
19/20
19/20
A
D
Q
ADDRESS
REGISTER
CE
CLK
36,18
or 72
36,18
or 72
GW
BWE
BW(a-h)
x18: a,b
x36: a-d
x72: a-h
DQ(a-d)
BYTE WRITE
REGISTERS
CLK
D
Q
CE
CE2
CE2
D
Q
2/4/8
ENABLE
REGISTER
CE
CLK
INPUT
REGISTERS
CLK
OE
36,18
or 72
DQa - DQd
ZZ
POWER
DOWN
OE
2
Integrated Silicon Solution, Inc.
Rev. K
07/29/2010
IS61LF25672A
IS61VF25672A
IS61LF51236A IS61LF102418A
IS61VF51236A IS61VF102418A
119-PIN BGA
119-Ball, 14x22 mm BGA
165-PIN BGA
165-Ball, 13x15 mm BGA
BOTTOM VIEW
BOTTOM VIEW
209-BALL BGA
209-Ball, 14 mm x 22 mm BGA
1 mm Ball Pitch, 11 x 19 Ball Array
BOTTOM VIEW
Integrated Silicon Solution, Inc.
Rev. K
07/29/2010
3
IS61LF25672A
IS61VF25672A
IS61LF51236A IS61LF102418A
IS61VF51236A IS61VF102418A
PIN CONFIGURATION — 256K X 72, 209-Ball PBGA (TOP VIEW)
1
2
3
4
5
6
7
8
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
DQg
DQg
DQg
DQg
DQPg
DQc
DQc
DQc
DQc
NC
DQh
DQh
DQh
DQh
DQPd
DQd
DQd
DQd
DQd
DQg
DQg
DQg
DQg
DQPc
DQc
DQc
DQc
DQc
NC
DQh
DQh
DQh
DQh
DQPh
DQd
DQd
DQd
DQd
A
BWc
BWh
VSS
V
DDQ
VSS
V
DDQ
VSS
V
DDQ
CLK
V
DDQ
VSS
V
DDQ
VSS
V
DDQ
VSS
NC
A
TMS
CE2
BWg
BWd
NC
V
DDQ
VSS
V
DDQ
VSS
V
DDQ
NC
V
DDQ
VSS
V
DDQ
VSS
V
DDQ
NC
A
A
TDI
ADSP
NC
NC
NC
V
DD
VSS
V
DD
VSS
V
DD
VSS
V
DD
VSS
V
DD
VSS
V
DD
NC
A
A
A
ADSC
BWE
CE
OE
V
DD
NC
NC
NC
NC
NC
NC
NC
NC
ZZ
V
DD
MODE
A
A1
A0
ADV
A
NC
GW
V
DD
VSS
V
DD
VSS
V
DD
VSS
V
DD
VSS
V
DD
VSS
V
DD
NC
A
A
A
CE2
BWb
BWe
NC
V
DDQ
VSS
V
DDQ
VSS
V
DDQ
NC
V
DDQ
VSS
V
DDQ
VSS
V
DDQ
NC
A
A
TDO
9
A
BWf
BWa
VSS
V
DDQ
VSS
V
DDQ
VSS
V
DDQ
NC
V
DDQ
VSS
V
DDQ
VSS
V
DDQ
VSS
NC
A
TCK
10
DQb
DQb
DQb
DQb
DQPf
DQf
DQf
DQf
DQf
NC
DQa
DQa
DQa
DQa
DQPa
DQe
DQe
DQe
DQe
11
DQb
DQb
DQb
DQb
DQPb
DQf
DQf
DQf
DQf
NC
DQa
DQa
DQa
DQa
DQPe
DQe
DQe
DQe
DQe
11 x 19 Ball BGA—14 x 22 mm
2
Body—1 mm Ball Pitch
PIN DESCRIPTIONS
Symbol
A
A0, A1
ADV
ADSP
ADSC
GW
CLK
CE, CE2,
CE2
BWx
(x=a,b,c,d
e,f,g,h)
Pin Name
Address Inputs
Synchronous Burst Address Inputs
Synchronous Burst Address
Advance
Address Status Processor
Address Status Controller
Global Write Enable
Synchronous Clock
Synchronous Chip Select
Synchronous Byte Write
Controls
Symbol
BWE
OE
ZZ
MODE
TCK, TDO
TMS, TDI
NC
DQx
DQPx
V
DD
V
DDQ
Vss
Pin Name
Byte Write Enable
Output Enable
Power Sleep Mode
Burst Sequence Selection
JTAG Pins
No Connect
Data Inputs/Outputs
Data Inputs/Outputs
3.3V/2.5V Power Supply
Isolated Output Power Supply
3.3V
/2.5V
Ground
4
Integrated Silicon Solution, Inc.
Rev. K
07/29/2010
IS61LF25672A
IS61VF25672A
IS61LF51236A IS61LF102418A
IS61VF51236A IS61VF102418A
119 BGA PACKAGE PIN CONFIGURATION-
512K
X
36 (TOP VIEW)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQc
DQc
V
DDQ
DQc
DQc
V
DDQ
DQd
DQd
V
DDQ
DQd
DQd
NC
NC
V
DDQ
2
A
A
A
DQPc
DQc
DQc
DQc
DQc
V
DD
DQd
DQd
DQd
DQd
DQPd
A
NC
TMS
3
A
A
A
Vss
Vss
Vss
BWc
Vss
NC
Vss
BWd
Vss
Vss
Vss
MODE
A
TDI
4
ADSP
ADSC
V
DD
NC
CE
OE
ADV
GW
V
DD
CLK
NC
BWE
A
1
*
A
0
*
V
DD
A
TCK
5
A
A
A
Vss
Vss
Vss
BWb
Vss
NC
Vss
BWa
Vss
Vss
Vss
NC
A
TDO
6
A
A
A
DQPb
DQb
DQb
DQb
DQb
V
DD
DQa
DQa
DQa
DQa
DQPa
A
NC
NC
7
V
DDQ
NC
NC
DQb
DQb
V
DDQ
DQb
DQb
V
DDQ
DQa
DQa
V
DDQ
DQa
DQa
NC
ZZ
V
DDQ
Note:
* A
0
and A
1
are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
A0, A1
ADV
ADSP
ADSC
GW
CLK
CE
BWE
Pin Name
Address Inputs
Synchronous Burst Address Inputs
Synchronous Burst Address
Advance.
Address Status Processor
Address Status Controller
Global Write Enable
Synchronous Clock
Synchronous Chip Select
Byte Write Enable
Symbol
OE
ZZ
MODE
TCK, TDO
TMS, TDI
NC
DQa-DQd
DQPa-Pd
V
DD
V
DDQ
Vss
Pin Name
Output Enable
Power Sleep Mode
Burst Sequence Selection
JTAG Pins
No Connect
Data Inputs/Outputs
Data Inputs/Outputs
Power Supply
Output Power Supply
Ground
BWx
(x=a-d) Synchronous Byte Write Controls
Integrated Silicon Solution, Inc.
Rev. K
07/29/2010
5
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