liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.- www.issi.com
Rev. D
07/31/2017
1
IS61LPS51236B/IS61VPS51236B/IS61VVPS51236B
IS61LPS102418B/IS61VPS102418B/IS61VVPS102418B
BLOCK DIAGRAM
Integrated Silicon Solution, Inc.- www.issi.com
Rev. D
07/31/2017
2
IS61LPS51236B/IS61VPS51236B/IS61VVPS51236B
IS61LPS102418B/IS61VPS102418B/IS61VVPS102418B
PIN CONFIGURATION
512K x 36, 165-Ball BGA (Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
2
3
4
5
6
7
8
9
10
11
NC
NC
DQPc
DQc
DQc
DQc
DQc
NC
DQd
DQd
DQd
DQd
DQPd
NC
MODE
A
A
NC
DQc
DQc
DQc
DQc
V
SS
DQd
DQd
DQd
DQd
NC
NC
NC
/CE
CE2
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
/BWc
/BWd
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
/BWb
/BWa
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
/CE2
CLK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
A1*
A0*
/BWE
/GW
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
TDO
TCK
/ADSC
/OE
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
/ADV
/ADSP
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
A
A
NC
DQb
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQa
NC
A
A
NC
NC
DQPb
DQb
DQb
DQb
DQb
ZZ
DQa
DQa
DQa
DQa
DQPa
A
A
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
CLK
A0,A1
A
/ADV
/ADSP
/ADSC
MODE
/CE,CE2,/CE2
/BWE
/BWx (x=a-d)
/GW
/OE
DQx
DQPx
TCK,TDI,
TDO,TMS
ZZ
NC
V
DD
V
DDQ
V
SS
Pin Name
Synchronous Clock
Synchronous Burst Address Inputs
Address Inputs
Synchronous Burst Address Advance
Address Status Processor
Address Status Controller
Burst Sequence Selection
Synchronous Chip Enable
Byte Write Enable
Synchronous Byte Write Inputs
Global Write Enable
Output Enable
Data Inputs/Outputs
Parity Data I/O
JTAG Pins
Power Sleep Mode
No Connect
Power Supply
I/O Power Supply
Ground
Bottom View
165-Ball, 13 mm x 15mm BGA
Integrated Silicon Solution, Inc.- www.issi.com
Rev. D
07/31/2017
3
IS61LPS51236B/IS61VPS51236B/IS61VVPS51236B
IS61LPS102418B/IS61VPS102418B/IS61VVPS102418B
1024K x 18, 165-Ball BGA (Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
2
3
4
5
6
7
8
9
10
11
NC
NC
NC
NC
NC
NC
NC
NC
DQb
DQb
DQb
DQb
DQPb
NC
MODE
A
A
NC
DQb
DQb
DQb
DQb
V
SS
NC
NC
NC
NC
NC
NC
NC
/CE
CE2
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
/BWb
NC
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
NC
/BWa
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
/CE2
CLK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
A1*
A0*
/BWE
/GW
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCK
/ADSC
/OE
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
/ADV
/ADSP
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
A
A
NC
NC
NC
NC
NC
NC
DQa
DQa
DQa
DQa
NC
A
A
A
NC
DQPa
DQa
DQa
DQa
DQa
ZZ
NC
NC
NC
NC
NC
A
A
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTION
Symbol
CLK
A0,A1
A
/ADV
/ADSP
/ADSC
MODE
CE, /CE, CE2
/BWE
/BWx (x=a-b)
/GW
/OE
DQx
TCK,TDI,
TDO,TMS
ZZ
NC
V
DD
V
DDQ
V
SS
Pin Name
Synchronous Clock
Synchronous Burst Address Inputs
Address Inputs
Synchronous Burst Address Advance
Address Status Processor
Address Status Controller
Burst Sequence Selection
Synchronous Chip Enable
Byte Write Enable
Synchronous Byte Write Inputs
Global Write Enable
Output Enable
Data Inputs/Outputs
JTAG Pins
Power Sleep Mode
No Connect
Power Supply
I/O Power Supply
Ground
Bottom View
165-Ball, 13 mm x 15mm BGA
Integrated Silicon Solution, Inc.- www.issi.com
Rev. D
07/31/2017
4
IS61LPS51236B/IS61VPS51236B/IS61VVPS51236B
IS61LPS102418B/IS61VPS102418B/IS61VVPS102418B
512K x 36, 119-Ball BGA (Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
2
3
4
5
6
7
V
DDQ
NC
NC
DQc
DQc
V
DDQ
DQc
DQc
V
DDQ
DQd
DQd
V
DDQ
DQd
DQd
NC
NC
V
DDQ
A
A
A
DQPc
DQc
DQc
DQc
DQc
V
DD
DQd
DQd
DQd
DQd
DQPd
A
NC
TMS
A
A
A
V
SS
V
SS
V
SS
/BWc
V
SS
NC
V
SS
/BWd
V
SS
V
SS
V
SS
MODE
A
TDI
/ADSP
/ADSC
V
DD
NC
/CE
/OE
/ADV
/GW
V
DD
CLK
NC
/BWE
A1*
A0*
VDD
A
TCK
A
A
A
V
SS
V
SS
V
SS
/BWb
V
SS
NC
V
SS
/BWa
V
SS
V
SS
V
SS
NC
A
TDO
A
A
A
DQPb
DQb
DQb
DQb
DQb
VDD
DQa
DQa
DQa
DQa
DQPa
A
NC
NC
V
DDQ
NC
NC
DQb
DQb
V
DDQ
DQb
DQb
V
DDQ
DQa
DQa
V
DDQ
DQa
DQa
NC
ZZ
V
DDQ
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
