IS61vPS25672A IS61lPS25672A
IS61vPS51236A IS61lPS51236A
IS61vPS102418A IS61lPS102418A
256K x 72, 512K x 36, 1024K x 18
18Mb SYNCHRONOUS PIPElINED,
SINglE CYClE DESElECT STATIC RAM
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Burst sequence control using MODE input
• Three chip enable option for simple depth ex-
pansion and address pipelining
• Common data inputs and data outputs
• Auto Power-down during deselect
• Single cycle deselect
• Snooze MODE for reduced-power standby
• JTAG Boundary Scan for PBGA package
• Power Supply
LPS: V
dd
3.3V + 5%,
V
ddq
3.3V/2.5V + 5%
VPS: V
dd
2.5V + 5%,
V
ddq
2.5V + 5%
• JEDEC 100-Pin TQFP, 119-ball PBGA, 165-ball
PBGA, and 209-ball (x72) packages
• Lead-free available
JUlY 2017
and IS61LPS/VPS25672A are high-speed, low-power
synchronous static
RAMs
designed to provide burstable,
high-performance
memory for communication and network-
ing applications. The IS61LPS/VPS51236A
is organized
as 524,288 words by 36 bits, the IS61LPS/VPS102418A
is
organized as 1,048,576 words by 18 bits, and the IS61LPS/
VPS25672A is organized as 262,144 words by 72 bits.
Fabricated with
ISSI
's advanced CMOS technology, the
device integrates a 2-bit burst counter, high-speed SRAM
core, and high-drive capability outputs into a single mono-
lithic circuit. All synchronous inputs pass through registers
controlled by a positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be one
to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
The byte write operation is performed by using the byte write
enable (BWE)
input combined with one or more individual
byte write signals (BWx). In addition, Global Write (GW)
is available for writing all bytes at one time, regardless of
the byte write controls.
Bursts can be initiated with either ADSP (Address Status
Processor) or
ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be gener-
ated internally and controlled by the
ADV (burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW. Interleave
burst is achieved when this pin is tied HIGH or left floating.
DESCRIPTION
The
ISSI
IS61LPS/VPS51236A, IS61LPS/VPS102418A,
FAST ACCESS TIME
Symbol
t
kq
t
kc
Parameter
Clock Access Time
Cycle Time
Frequency
250
2.6
4
250
200
3.1
5
200
Units
ns
ns
MHz
Copyright © 2017 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. Q
07/19/2017
1
IS61VPS25672A, IS61LPS25672A
IS61VPS51236A, IS61LPS51236A, IS61VPS102418A, IS61LPS102418A
BLOCK DIAGRAM
MODE
CLK
CLK
Q0
A0
A0'
BINARY
COUNTER
ADV
ADSC
ADSP
CE
CLR
Q1
A1
A1'
256Kx72;
512Kx36;
1024Kx18
MEMORY ARRAY
19/20
A
19/20
D
Q
17/18
ADDRESS
REGISTER
CE
CLK
36,
or 18
or 72
36,
or 18
or 72
GW
BWE
BW(a-h)
x18: a,b
x36: a-d
x72: a-h
DQ(a-h)
BYTE WRITE
REGISTERS
CLK
D
Q
CE
CE2
CE2
D
Q
2/4/8
ENABLE
REGISTER
CE
CLK
INPUT
REGISTERS
CLK
OUTPUT
REGISTERS
CLK
36,
or 18
or 72
DQa - DQd
OE
D
Q
ZZ
POWER
DOWN
ENABLE
DELAY
REGISTER
CLK
OE
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. Q
07/19/2017
IS61VPS25672A, IS61LPS25672A
IS61VPS51236A, IS61LPS51236A, IS61VPS102418A, IS61LPS102418A
165-PIN BgA
165-Ball, 13x15 mm BGA
1mm Ball Pitch, 11x15 Ball Array
119-PIN BgA
119-Ball, 14x22 mm BGA
1mm Ball Pitch, 7x17 Ball Array
BOTTOM VIEW
BOTTOM VIEW
209-BAll BgA
209-Ball, 14 mm x 22 mm BGA
1 mm Ball Pitch, 11 x 19 Ball Array
BOTTOM VIEW
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. Q
07/19/2017
3
IS61VPS25672A, IS61LPS25672A
IS61VPS51236A, IS61LPS51236A, IS61VPS102418A, IS61LPS102418A
PIN CONFIgURATION — 256K x 72, 209-Ball PBgA (TOP vIEw)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
DQg
DQg
DQg
DQg
DQPg
DQc
DQc
DQc
DQc
NC
DQh
DQh
DQh
DQh
DQPd
DQd
DQd
DQd
DQd
2
DQg
DQg
DQg
DQg
DQPc
DQc
DQc
DQc
DQc
NC
DQh
DQh
DQh
DQh
DQPh
DQd
DQd
DQd
DQd
3
A
BWc
BWh
VSS
V
ddq
VSS
V
ddq
VSS
V
ddq
CLK
V
ddq
VSS
V
ddq
VSS
V
ddq
VSS
NC
A
TMS
4
CE2
BWg
BWd
NC
V
ddq
VSS
V
ddq
VSS
V
ddq
NC
V
ddq
VSS
V
ddq
VSS
V
ddq
NC
A
A
TDI
5
ADSP
NC
NC
NC
V
dd
VSS
V
dd
VSS
V
dd
VSS
V
dd
VSS
V
dd
VSS
V
dd
NC
A
A
A
6
ADSC
BWE
CE
OE
V
dd
NC
NC
NC
NC
NC
NC
NC
NC
ZZ
V
dd
MODE
A
A1
A0
7
ADV
A
NC
GW
V
dd
VSS
V
dd
VSS
V
dd
VSS
V
dd
VSS
V
dd
VSS
V
dd
NC
A
A
A
8
CE2
BWb
BWe
NC
V
ddq
VSS
V
ddq
VSS
V
ddq
NC
V
ddq
VSS
V
ddq
VSS
V
ddq
NC
A
A
TDO
9
A
BWf
BWa
VSS
V
ddq
VSS
V
ddq
VSS
V
ddq
NC
V
ddq
VSS
V
ddq
VSS
V
ddq
VSS
NC
A
TCK
10
DQb
DQb
DQb
DQb
DQPf
DQf
DQf
DQf
DQf
NC
DQa
DQa
DQa
DQa
DQPa
DQe
DQe
DQe
DQe
11
DQb
DQb
DQb
DQb
DQPb
DQf
DQf
DQf
DQf
NC
DQa
DQa
DQa
DQa
DQPe
DQe
DQe
DQe
DQe
11 x 19 Ball BGA—14 x 22 mm
2
Body—1 mm Ball Pitch
PIN DESCRIPTIONS
Symbol
A
A0, A1
ADV
ADSP
ADSC
GW
CLK
CE, CE2,
CE2
BWx (x=a,b,c,d
e,f,g,h)
Pin Name
Address Inputs
Synchronous Burst Address Inputs
Synchronous Burst Address
Advance
Address Status Processor
Address Status Controller
Global Write Enable
Synchronous Clock
Synchronous Chip Select
Synchronous Byte Write
Controls
Symbol
BWE
OE
ZZ
MODE
TCK, TDO
TMS, TDI
NC
DQx
DQPx
V
dd
V
ddq
Vss
Pin Name
Byte Write Enable
Output Enable
Power Sleep Mode
Burst Sequence Selection
JTAG Pins
No Connect
Data Inputs/Outputs
Data Inputs/Outputs
3.3V/2.5V Power Supply
Isolated Output Power Supply
3.3V
/2.5V
Ground
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. Q
07/19/2017
IS61VPS25672A, IS61LPS25672A
IS61VPS51236A, IS61LPS51236A, IS61VPS102418A, IS61LPS102418A
119 BGA PACKAGE PIN CONFIGURATION-
512k
x
36 (TOP VIEW)
1
A
B
C
D
E
F
g
H
J
K
l
M
N
P
R
T
U
V
DDQ
NC
NC
DQc
DQc
V
DDQ
DQc
DQc
V
DDQ
DQd
DQd
V
DDQ
DQd
DQd
NC
NC
V
DDQ
2
A
A
A
DQPc
DQc
DQc
DQc
DQc
V
DD
DQd
DQd
DQd
DQd
DQPd
A
NC
TMS
3
A
A
A
Vss
Vss
Vss
BWc
Vss
NC
Vss
BWd
Vss
Vss
Vss
MODE
A
TDI
4
ADSP
ADSC
V
DD
NC
CE
OE
ADV
GW
V
DD
CLK
NC
BWE
A
1
*
A
0
*
V
DD
A
TCK
5
A
A
A
Vss
Vss
Vss
BWb
Vss
NC
Vss
BWa
Vss
Vss
Vss
NC
A
TDO
6
A
A
A
DQPb
DQb
DQb
DQb
DQb
V
DD
DQa
DQa
DQa
DQa
DQPa
A
NC
NC
7
V
DDQ
NC
NC
DQb
DQb
V
DDQ
DQb
DQb
V
DDQ
DQa
DQa
V
DDQ
DQa
DQa
NC
ZZ
V
DDQ
Note:
* A
0
and A
1
are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
A0, A1
ADV
ADSP
ADSC
GW
CLK
CE
BWE
Pin Name
Address Inputs
Synchronous Burst Address Inputs
Synchronous Burst Address
Advance
Address Status Processor
Address Status Controller
Global Write Enable
Synchronous Clock
Synchronous Chip Select
Byte Write Enable
Symbol
OE
ZZ
MODE
TCK, TDO
TMS, TDI
NC
DQa-DQd
DQPa-Pd
V
dd
V
ddq
Vss
No Connect
Data Inputs/Outputs
Output Power Supply
Power Supply
Output Power Supply
Ground
Pin Name
Output Enable
Power Sleep Mode
Burst Sequence Selection
JTAG Pins
BWx (x=a-d)
Synchronous Byte Write Controls
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. Q
07/19/2017
5
