IS61LV25616
FEATURES
256K x 16 HIGH SPEED ASYNCHRONOUS
CMOS STATIC RAM WITH 3.3V SUPPLY
High-speed access time: 8, 10, 12, and 15 ns
CMOS low power operation
TTL compatible interface levels
Single 3.3V ± 10% power supply
Fully static operation: no clock or refresh
required
Three state outputs
Data control for upper and lower bytes
Industrial temperature available
DESCRIPTION
The
1+51
IS61LV25616 is a high-speed, 4,194,304-bit static
RAM organized as 262,144 words by 16 bits. It is fabricated
using
1+51
's high-performance CMOS technology. This highly
reliable process coupled with innovative circuit design
techniques, yields high-performance and low power consump-
tion devices.
When
CE
is HIGH (deselected), the device assumes a standby
mode at which the power dissipation can be reduced down with
CMOS input levels.
Easy memory expansion is provided by using Chip Enable and
Output Enable inputs,
CE
and
OE.
The active LOW Write
Enable (WE) controls both writing and reading of the memory.
A data byte allows Upper Byte (UB) and Lower Byte (LB)
access.
The IS61LV25616 is packaged in the JEDEC standard
44-pin 400mil SOJ, 44 pin 400mil TSOP-2 and 48-pin 6*8 TF-
BGA.
FUNCTIONAL BLOCK DIAGRAM
A0-A17
DECODER
256K x 16
MEMORY ARRAY
VCC
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
I/O
DATA
CIRCUIT
COLUMN I/O
CE
OE
WE
UB
LB
CONTROL
CIRCUIT
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
SR040-0C
1
IS61LV25616
PIN CONFIGURATIONS
44-Pin TSOP-2 and SOJ
48-Pin TF-BGA
1
2
OE
UB
I/O
2
I/O
3
I/O
4
I/O
5
NC
A8
3
A0
A3
A5
A17
NC
A14
A12
A9
4
A1
A4
A6
A7
A16
A15
A13
A10
5
A2
CE
I/O
10
I/O
11
I/O
12
I/O
13
WE
A11
6
N/C
I/O
8
I/O
9
Vcc
GND
I/O
14
I/O
15
NC
A0
A1
A2
A3
A4
CE
I/O0
I/O1
I/O2
I/O3
Vcc
GND
I/O4
I/O5
I/O6
I/O7
WE
A5
A6
A7
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
A16
A15
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A14
A13
A12
A11
A10
A
B
C
D
E
F
G
H
LB
I/O
0
I/O
1
GND
Vcc
I/O
6
I/O
7
NC
PIN DESCRIPTIONS
A0-A17
I/O0-I/O15
CE
OE
WE
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Output Enable Input
Write Enable Input
LB
UB
NC
Vcc
GND
Lower-byte Control (I/O0-I/O7)
Upper-byte Control (I/O8-I/O15)
No Connection
Power
Ground
TRUTH TABLE
Mode
Not Selected
Output Disabled
Read
WE
X
H
X
H
H
H
L
L
L
CE
H
L
L
L
L
L
L
L
L
OE
X
H
X
L
L
L
X
X
X
LB
X
X
H
L
H
L
L
H
L
UB
X
X
H
H
L
L
H
L
L
I/O PIN
I/O0-I/O7 I/O8-I/O15
High-Z
High-Z
High-Z
D
OUT
High-Z
D
OUT
D
IN
High-Z
D
IN
High-Z
High-Z
High-Z
High-Z
D
OUT
D
OUT
High-Z
D
IN
D
IN
Vcc Current
I
SB
, I
SB
I
CC
I
CC
Write
I
CC
2
Integrated Circuit Solution Inc.
SR040-0C
IS61LV25616
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
T
BIAS
V
CC
T
STG
P
T
Parameter
Terminal Voltage with Respect to GND
Temperature Under Bias
Vcc Related to GND
Storage Temperature
Power Dissipation
Value
0.5 to Vcc+0.5
45 to +90
0.3 to +4.0
65 to +150
1.0
Unit
V
°C
V
°C
W
Note:
1. Stress greater than those listed under
ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device.
This is a stress rating only and func-
tional operation of the device at these
or any other conditions above those
indicated in the operational sections of
this specification is not implied. Expo-
sure to absolute maximum rating con-
ditions for extended periods may affect
reliability.
OPERATING RANGE
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
40°C to +85°C
V
CC
3.3V ± 10%
3.3V ± 10%
!
"
Min.
2.4
2.0
0.3
GND < V
IN
< V
CC
GND < V
OUT
< V
CC
Outputs Disabled
Com.
Ind.
Com.
Ind.
1
5
1
5
Max.
0.4
V
CC
+ 0.3
0.8
1
5
1
5
Unit
V
V
V
V
µA
µA
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
Symbol
V
OH
V
OL
V
IH
V
IL
I
LI
I
LO
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
(1)
Input Leakage
Output Leakage
Test Conditions
V
CC
= Min., I
OH
= 4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
#
$
%
&
'
Notes:
1. V
IL
(min.) = 2.0V for pulse width less than 10 ns.
2. The Vcc operating range for 8 ns is 3.3V +10%, -5%.
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
Symbol
I
CC
I
SB
Parameter
Vcc Dynamic Operating
Supply Current
TTL Standby Current
(TTL Inputs)
CMOS Standby
Current (CMOS Inputs)
Test Conditions
V
CC
= Max.,
I
OUT
= 0 mA, f = f
MAX
V
CC
= Max.,
V
IN
= V
IH
or V
IL
CE
≥
V
IH
, f = 0
V
CC
= Max.,
CE
≥
V
CC
0.2V,
V
IN
≥
V
CC
0.2V, or
V
IN
≤
0.2V, f = 0
Com.
Ind.
Com.
Ind.
Com.
Ind.
-8 ns
Min. Max.
350
360
55
65
10
15
-10 ns
Min. Max.
320
330
55
65
10
15
-12 ns
Min. Max.
290
300
55
65
10
15
-15 ns
Min. Max.
260
270
55
65
10
15
Unit
mA
mA
3
I
SB
mA
Note:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
Integrated Circuit Solution Inc.
SR040-0C
IS61LV25616
CAPACITANCE
(1)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Input/Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
6
8
Unit
pF
pF
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
Symbol
Parameter
Read Cycle Time
Address Access Time
Output Hold Time
CE
Access Time
OE
Access Time
Min.
8
3
0
0
0
3
0
0
-8
Max.
8
8
4
4
4
4
4
-10
Min. Max.
10
3
0
0
3
0
0
10
10
5
5
5
5
5
-12
Min. Max.
12
3
0
0
3
0
0
12
12
6
6
6
6
6
-15
Min. Max.
15
3
0
0
0
3
0
0
15
15
7
6
6
7
6
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
HZOE
OE
to High-Z Output
t
LZOE
OE
to Low-Z Output
t
HZCE
t
BA
t
HZB
t
LZB
CE
to High-Z Output
LB, UB
Access Time
LB, UB
to High-Z Output
LB, UB
to Low-Z Output
t
LZCE
CE
to Low-Z Output
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of
0 to 3.0V and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 3.0V
3 ns
1.5V
See Figures 1 and 2
Notes:
1. The Vcc operating range for 8 ns is 3.3V +10%, -5%.
AC TEST LOADS
3.3V
319
Ω
3.3V
319
Ω
OUTPUT
30 pF
Including
jig and
scope
353
Ω
OUTPUT
5 pF
Including
jig and
scope
353
Ω
Figure 1
4
Figure 2
Integrated Circuit Solution Inc.
SR040-0C
IS61LV25616
AC WAVEFORMS
READ CYCLE NO. 1
(1,2)
(Address Controlled) (CE =
OE
= V
IL
,
UB
or
LB
= V
IL
)
t
RC
ADDRESS
t
OHA
DATA VALID
t
AA
t
OHA
D
OUT
PREVIOUS DATA VALID
!
"
READ CYCLE NO. 2
(1,3)
t
RC
ADDRESS
t
AA
t
OHA
#
$
%
t
HZCE
t
HZB
DATA VALID
OE
t
DOE
t
HZOE
CE
t
LZCE
t
LZOE
t
ACE
LB, UB
t
BA
t
LZB
&
'
D
OUT
HIGH-Z
Notes:
1.
WE
is HIGH for a Read Cycle.
2. The device is continuously selected.
OE, CE, UB,
or
LB
= V
IL
.
3. Address is valid prior to or coincident with
CE
LOW transition.
Integrated Circuit Solution Inc.
SR040-0C
5
模拟与混合信号
