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IS61LV5128AL-10K-TR

SRAM Chip Async Single 3.3V 4M-bit 512K x 8 10ns 36-Pin SOJ T/R

厂商名称:ISSI(芯成半导体)

厂商官网:http://www.issi.com/

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器件参数
参数名称
属性值
欧盟限制某些有害物质的使用
Not Compliant
ECCN (US)
EAR99
Part Status
Active
HTS
8542.39.00.01
Chip Density (bit)
4M
Number of Words
512K
Number of Bits/Word (bit)
8
Data Rate Architecture
SDR
Address Bus Width (bit)
19
Number of Ports
1
Timing Type
Asynchronous
Max. Access Time (ns)
10
Minimum Operating Supply Voltage (V)
3.135
Typical Operating Supply Voltage (V)
3.3
Maximum Operating Supply Voltage (V)
3.63
Operating Current (mA)
90
Minimum Operating Temperature (°C)
0
Maximum Operating Temperature (°C)
70
Supplier Temperature Grade
Commercial
系列
Packaging
Tape and Reel
Supplier Package
SOJ
Pin Count
36
Standard Package Name
SOJ
Mounting
Surface Mount
Package Height
3.75(Max) - 0.64(Min)
Package Length
23.62(Max)
Package Width
10.29(Max)
PCB changed
36
Lead Shape
J-Lead
参考设计
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IS61LV5128AL
512K x 8 HIGH-SPEED CMOS STATIC RAM
ISSI
APRIL 2005
®
FEATURES
• High-speed access times:
10, 12 ns
• High-performance, low-power CMOS process
• Multiple center power and ground pins for
greater noise immunity
• Easy memory expansion with
CE
and
OE
options
CE
power-down
• Fully static operation: no clock or refresh
required
• TTL compatible inputs and outputs
• Single 3.3V power supply
• Packages available:
– 36-pin 400-mil SOJ
– 36-pin miniBGA
– 44-pin TSOP (Type II)
• Lead-free available
DESCRIPTION
The
ISSI
IS61LV5128AL is a very high-speed, low power,
524,288-word by 8-bit CMOS static RAM. The
IS61LV5128AL is fabricated using
ISSI
's high-perform-
ance CMOS technology. This highly reliable process
coupled with innovative circuit design techniques, yields
higher performance and low power consumption devices.
When
CE
is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down to 250 µW (typical) with CMOS input levels.
The IS61LV5128AL operates from a single 3.3V power
supply and all inputs are TTL-compatible.
The IS61LV5128AL is available in 36-pin 400-mil SOJ, 36-
pin mini BGA, and 44-pin TSOP (Type II) packages.
FUNCTIONAL BLOCK DIAGRAM
A0-A18
DECODER
512K X 8
MEMORY ARRAY
V
DD
GND
I/O
DATA
CIRCUIT
I/O0-I/O7
COLUMN I/O
CE
OE
WE
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
CONTROL
CIRCUIT
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. C
04/15/05
1
IS61LV5128AL
PIN CONFIGURATION
36 mini BGA
44-Pin TSOP (Type II)
ISSI
3
4
5
6
®
1
2
A
B
C
D
E
F
G
H
A0
I/O4
I/O5
GND
V
DD
I/O6
I/O7
A9
A1
A2
NC
WE
NC
A3
A4
A5
A6
A7
A8
I/O0
I/O1
V
DD
GND
A18
OE
A10
CE
A11
A17
A16
A12
A15
A13
I/O2
I/O3
A14
NC
NC
A0
A1
A2
A3
A4
CE
I/O0
I/O1
V
DD
GND
I/O2
I/O3
WE
A5
A6
A7
A8
A9
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
NC
A18
A17
A16
A15
OE
I/O7
I/O6
GND
V
DD
I/O5
I/O4
A14
A13
A12
A11
A10
NC
NC
NC
PIN DESCRIPTIONS
A0-A18
CE
OE
WE
I/O0-I/O7
V
DD
GND
NC
Address Inputs
Chip Enable Input
Output Enable Input
Write Enable Input
Bidirectional Ports
Power
Ground
No Connection
36-Pin SOJ
A0
A1
A2
A3
A4
CE
I/O0
I/O1
V
DD
GND
I/O2
I/O3
WE
A5
A6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
A18
A17
A16
A15
OE
I/O7
I/O6
GND
V
DD
I/O5
I/O4
A14
A13
A12
A11
A10
NC
TRUTH TABLE
Mode
WE
X
H
H
L
CE
H
L
L
L
OE
X
H
L
X
I/O Operation
High-Z
High-Z
D
OUT
D
IN
V
DD
Current
I
SB
1
, I
SB
2
I
CC
I
CC
I
CC
Not Selected
(Power-down)
Output Disabled
Read
Write
A7
A8
A9
2
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. C
04/15/05
IS61LV5128AL
ISSI
Value
–0.5 to V
DD
+ 0.5
–65 to +150
1.0
Unit
V
°C
W
®
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
T
STG
P
T
Parameter
Terminal Voltage with Respect to GND
Storage Temperature
Power Dissipation
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause perma-
nent damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
OPERATING RANGE
V
DD
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
-40°C to +85°C
10ns
3.3V +10%, -5%
3.3V +10%, -5%
12ns
3.3V +10%
3.3V +10%
CAPACITANCE
(1,2)
Symbol
C
IN
C
I/O
Parameter
Input Capacitance
Input/Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
6
8
Unit
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25°C, f = 1 MHz, V
DD
= 3.3V.
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. C
04/15/05
3
IS61LV5128AL
ISSI
Test Conditions
V
DD
= Min., I
OH
= –4.0 mA
V
DD
= Min., I
OL
= 8.0 mA
Min.
2.4
2.0
–0.3
GND
V
IN
V
DD
GND
V
OUT
V
DD
, Outputs Disabled
Com.
Ind.
Com.
Ind.
–2
–5
–2
–5
Max.
0.4
V
DD
+ 0.3
0.8
2
5
2
5
Unit
V
V
V
V
µA
µA
®
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
Symbol Parameter
V
OH
V
OL
V
IH
V
IL
I
LI
I
LO
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
(1)
Input Leakage
Output Leakage
Note:
1. V
IL
= –3.0V for pulse width less than 10 ns.
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
Symbol Parameter
I
CC
I
SB
V
DD
Dynamic Operating
Supply Current
TTL Standby Current
(TTL Inputs)
TTL Standby Current
(TTL Inputs)
CMOS Standby
Current (CMOS Inputs)
Test Conditions
V
DD
= Max.,
Com.
I
OUT
= 0 mA, f = f
MAX
Ind.
V
DD
= Max.,
V
IN
= V
IH
or V
IL
CE
V
IH
, f = f
MAX
.
V
DD
= Max.,
V
IN
= V
IH
or V
IL
CE
V
IH
, f = 0
Com.
Ind.
Com.
Ind.
-10
Min. Max.
90
95
40
45
20
25
15
20
-12
Min. Max.
85
90
35
40
20
25
15
20
Unit
mA
mA
I
SB
1
mA
I
SB
2
V
DD
= Max.,
Com.
CE
V
DD
– 0.2V,
Ind.
V
IN
V
DD
– 0.2V, or
V
IN
0.2V, f = 0
mA
Note:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
4
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. C
04/15/05
IS61LV5128AL
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
Symbol
Parameter
Read Cycle Time
Address Access Time
Output Hold Time
CE
Access Time
OE
Access Time
OE
to High-Z Output
OE
to Low-Z Output
CE
to High-Z Output
CE
to Low-Z Output
Power Up Time
Power Down Time
-10
Min. Max.
10
2
0
0
3
0
10
10
4
4
4
10
-12
Min. Max.
12
2
0
0
3
0
12
12
5
5
6
12
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ISSI
®
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
HZOE
(2)
t
LZOE
(2)
t
HZCE
(2
t
LZCE
(2)
t
PU
t
PD
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse
levels of 0V to 3.0V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Levels
Output Load
Unit
0V to 3.0V
3 ns
1.5V
See Figures 1 and 2
AC TEST LOADS
319
3.3V
3.3V
319
OUTPUT
30 pF
Including
jig and
scope
353
OUTPUT
5 pF
Including
jig and
scope
353
Figure 1
Figure 2
5
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. C
04/15/05
查看更多>
参数对比
与IS61LV5128AL-10K-TR相近的元器件有:IS61LV5128AL-10K、IS61LV5128AL-10TLI-TR、IS61LV5128AL-10KLI-TR、IS61LV5128AL-10TLI。描述及对比如下:
型号 IS61LV5128AL-10K-TR IS61LV5128AL-10K IS61LV5128AL-10TLI-TR IS61LV5128AL-10KLI-TR IS61LV5128AL-10TLI
描述 SRAM Chip Async Single 3.3V 4M-bit 512K x 8 10ns 36-Pin SOJ T/R SRAM Chip Async Single 3.3V 4M-bit 512K x 8 10ns 36-Pin SOJ SRAM Chip Async Single 3.3V 4M-bit 512K x 8 10ns 44-Pin TSOP-II T/R SRAM Chip Async Single 3.3V 4M-bit 512K x 8 10ns 36-Pin SOJ T/R SRAM Chip Async Single 3.3V 4M-bit 512K x 8 10ns 44-Pin TSOP-II
欧盟限制某些有害物质的使用 Not Compliant - Compliant - Compliant
ECCN (US) EAR99 - 3A991.b.2.a - EAR99
Part Status Active - Active - Unconfirmed
HTS 8542.39.00.01 - 8542.32.00.41 - 8542.32.00.41
Chip Density (bit) 4M - 4M - 4M
Number of Words 512K - 512K - 512K
Number of Bits/Word (bit) 8 - 8 - 8
Data Rate Architecture SDR - SDR - SDR
Address Bus Width (bit) 19 - 19 - 19
Number of Ports 1 - 1 - 1
Timing Type Asynchronous - Asynchronous - Asynchronous
Max. Access Time (ns) 10 - 10 - 10
Minimum Operating Supply Voltage (V) 3.135 - 3.135 - 3.135
Typical Operating Supply Voltage (V) 3.3 - 3.3 - 3.3
Maximum Operating Supply Voltage (V) 3.63 - 3.63 - 3.63
Operating Current (mA) 90 - 95 - 95
Maximum Operating Temperature (°C) 70 - 85 - 85
Supplier Temperature Grade Commercial - Industrial - Industrial
Supplier Package SOJ - TSOP-II - TSOP-II
Pin Count 36 - 44 - 44
Standard Package Name SOJ - SOP - SOP
Mounting Surface Mount - Surface Mount - Surface Mount
Package Height 3.75(Max) - 0.64(Min) - 1.05(Max) - 1.05(Max)
Package Length 23.62(Max) - 18.52(Max) - 18.52(Max)
Package Width 10.29(Max) - 10.29(Max) - 10.29(Max)
PCB changed 36 - 44 - 44
Lead Shape J-Lead - Gull-wing - Gull-wing
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00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W
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