without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
01/15/04
1
IS61LV6464
BLOCK DIAGRAM
ISSI
MODE
Q0
A0'
®
CLK
CLK
A0
BINARY
COUNTER
ADV
ADSC
ADSP
CE
CLR
Q1
A1'
A1
64K x 64
MEMORY
ARRAY
14
16
A15-A0
16
D
Q
ADDRESS
REGISTER
CE
CLK
64
64
GW
BWE
BW8
D
Q
DQ57-DQ64
BYTE WRITE
REGISTERS
CLK
D
BW1
Q
DQ8-DQ1
BYTE WRITE
REGISTERS
CLK
CE
CE2
CE2
CE3
CE3
D
Q
8
ENABLE
REGISTER
CE
CLK
INPUT
REGISTERS
CLK
OUTPUT
REGISTERS
CLK
OE
64
DATA[64:1]
D
Q
ENABLE
DELAY
REGISTER
CLK
OE
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
01/15/04
IS61LV6464
PIN CONFIGURATION
128-Pin TQFP/PQFP
VDDQ
CE3
CE2
CE3
CE2
GND
VDD
CE
BW8
BW7
BW6
BW5
OE
CLK
BWE
GW
BW4
BW3
GND
VDD
BW2
BW1
ADSC
ADSP
ADV
GNDQ
ISSI
®
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
GNDQ
I/O
33
I/O
34
I/O
35
I/O
36
I/O
37
I/O
38
I/O
39
I/O
40
I/O
41
I/O
42
I/O
43
VDDQ
GNDQ
I/O
44
I/O
45
I/O
46
I/O
47
I/O
48
I/O
49
I/O
50
I/O
51
I/O
52
I/O
53
VDDQ
GNDQ
I/O
54
I/O
55
I/O
56
I/O
57
I/O
58
I/O
59
I/O
60
I/O
61
I/O
62
I/O
63
I/O
64
VDDQ
PIN DESCRIPTIONS
A0-A15
CLK
ADSP
ADSC
ADV
BW1-BW8
BWE
GW
CE,
CE2,
CE2,
CE3,
CE3
OE
Address Inputs
Clock
Processor Address Status
Controller Address Status
Burst Address Advance
Synchronous Byte Write Enable
Byte Write Enable
Global Write Enable
Synchronous Chip Enable
Output Enable
NC
GND
Q
DQ1-DQ64
ZZ
MODE
V
DD
GND
V
DDQ
Data Input/Output
Sleep Mode
Burst Sequence Mode
+3.3V Power Supply
Ground
Isolated Output Buffer Supply:
+2.5V
No Connect
Isolated Output Buffer Ground
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
01/15/04
GNDQ
NC
MODE
A15
A14
A13
VDD
GND
A12
A11
A10
A9
A8
NC
A7
A6
A5
A4
A3
VDD
GND
A2
A1
A0
ZZ
VDDQ
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
VDDQ
I/O
32
I/O
31
I/O
30
I/O
29
I/O
28
I/O
27
I/O
26
I/O
25
I/O
24
I/O
23
I/O
22
GNDQ
VDDQ
I/O
21
I/O
20
I/O
19
I/O
18
I/O
17
I/O
16
I/O
15
I/O
14
I/O
13
I/O
12
GNDQ
VDDQ
I/O
11
I/O
10
I/O
9
I/O
8
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
I/O
2
I/O
1
GNDQ
3
IS61LV6464
TRUTH TABLE
OPERATION
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
ADDRESS
USED
CE3
None
None
None
None
None
None
None
None
None
External
External
External
External
External
Next
Next
Next
Next
Next
Next
Current
Current
Current
Current
Current
Current
X
L
X
X
X
L
X
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
CE2
X
X
L
X
X
X
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
CE3
X
X
X
H
X
X
X
H
X
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
CE2
X
X
X
X
H
X
X
X
H
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
CE
H
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
H
H
X
H
X
X
H
H
X
H
ADSP ADSC ADV WRITE
X
L
L
L
L
H
H
H
H
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L
X
X
X
X
L
L
L
L
X
X
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
L
H
H
H
H
H
H
L
L
H
H
H
H
L
L
ISSI
OE
CLK
X
X
X
X
X
X
X
X
X
L
H
X
L
H
L
H
L
H
X
X
L
H
L
H
X
X
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
I/O
®
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Dout
High-Z
Din
Dout
High-Z
Dout
High-Z
Dout
High-Z
Din
Din
Dout
High-Z
Dout
High-Z
Din
Din
Notes:
1. All inputs except
OE
must meet setup and hold times for the Low-to-High transition of clock (CLK).
2. Wait states are inserted by suspending burst.
3. X means don't care.
WRITE=L
means any one or more byte write enable signals (BW1-BW8) and
BWE
are LOW or
GW
is LOW.
WRITE=H
means all byte write enable signals are HIGH.
4. For a Write operation following a Read operation,
OE
must be HIGH before the input data required setup time and held HIGH
throughout the input data hold time.
5.
ADSP
LOW always initiates an internal READ at the Low-to-High edge of clock. A WRITE is performed by setting one or more
byte write enable signals and
BWE
LOW or
GW
LOW for the subsequent L-H edge of clock.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
01/15/04
IS61LV6464
TRUTH TABLE
Operation
Pipelined
Read
Pipelined
Read
Write
Write
Deselect
Sleep
ZZ
L
L
L
L
L
H
OE
ISSI
I/O STATUS
Dout
High-Z
High-Z
Din
High-Z
High-Z
L
H
L
H
X
X
®
WRITE TRUTH TABLE
Operation
Read
Read
Write all bytes
Write all bytes
Write Byte 1
Write Byte 2
Write Byte 3
Write Byte 4
Write Byte 5
Write Byte 6
Write Byte 7
Write Byte 8
GW
H
H
H
L
H
H
H
H
H
H
H
H
BWE
H
L
L
X
L
L
L
L
L
L
L
L
BW8
X
H
L
X
H
H
H
H
H
H
H
L
BW7
X
H
L
X
H
H
H
H
H
H
L
H
BW6
X
H
L
X
H
H
H
H
H
L
H
H
BW5
X
H
L
X
H
H
H
H
L
H
H
H
BW4
X
H
L
X
H
H
H
L
H
H
H
H
BW3
X
H
L
X
H
H
L
H
H
H
H
H
BW2
X
H
L
X
H
L
H
H
H
H
H
H
BW1
X
H
L
X
L
H
H
H
H
H
H
H
Integrated Silicon Solution, Inc. — 1-800-379-4774
