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IS61NLF51218A-6.5B2I

512K X 18 ZBT SRAM, 7.5 ns, PQFP100
512K × 18 ZBT 静态随机存储器, 7.5 ns, PQFP100

器件类别：存储   

厂商名称：ISSI(芯成半导体)

厂商官网：http://www.issi.com/

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参数 预览
器件参数
参数名称
属性值
功能数量
1
端子数量
100
最大工作温度
85 Cel
最小工作温度
-40 Cel
最大供电/工作电压
3.46 V
最小供电/工作电压
3.14 V
额定供电电压
3.3 V
最大存取时间
7.5 ns
加工封装描述
14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, TQFP-100
无铅
Yes
欧盟RoHS规范
Yes
状态
ACTIVE
工艺
CMOS
包装形状
RECTANGULAR
包装尺寸
FLATPACK, LOW PROFILE
表面贴装
Yes
端子形式
GULL WING
端子间距
0.6500 mm
端子涂层
MATTE TIN
端子位置
QUAD
包装材料
PLASTIC/EPOXY
温度等级
INDUSTRIAL
内存宽度
18
组织
512K X 18
存储密度
9.44E6 deg
操作模式
SYNCHRONOUS
位数
524288 words
位数
512K
内存IC类型
ZBT SRAM
串行并行
PARALLEL
文档预览
IS61NLF25636A/IS61NVF25636A
IS61NLF51218A/IS61NVF51218A 
 
256K x 36 and 512K x 18
9Mb, FLOW THROUGH 'NO WAIT' STATE BUS SRAM
AUGUST 2011
FEATURES
• 100 percent bus utilization
• No wait cycles between Read and Write
• Internal self-timed write cycle
• Individual Byte Write Control
• Single Read/Write control pin
• Clock controlled, registered address,
data and control
DESCRIPTION
The 9 Meg 'NLF/NVF' product family feature high-speed,
low-power synchronous static RAMs designed to provide
a burstable, high-performance, 'no wait' state, device for
networking and communications applications. They are
organized as 256K words by 36 bits and 512K words by
18 bits, fabricated with
ISSI
's advanced CMOS technology.
Incorporating a 'no wait' state feature, wait cycles are
eliminated when the bus switches from read to write, or
write to read. This device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs
into a single monolithic circuit.
All synchronous inputs pass through registers are controlled
by a positive-edge-triggered single clock input. Operations
may be suspended and all synchronous inputs ignored
when Clock Enable, CKE is HIGH. In this state the internal
device will hold their previous values.
All Read, Write and Deselect cycles are initiated by the ADV
input. When the ADV is HIGH the internal burst counter
is incremented. New external addresses can be loaded
when ADV is LOW.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock inputs and when WE is LOW.
Separate byte enables allow individual bytes to be written.
A burst mode pin (MODE) defines the order of the burst
sequence. When tied HIGH, the interleaved burst sequence
is selected. When tied LOW, the linear burst sequence is
selected.
• Interleaved or linear burst sequence control us-
ing MODE input
• Three chip enables for simple depth expansion
and address pipelining
• Power Down mode
• Common data inputs and data outputs
•
CKE pin to enable clock and suspend operation
• JEDEC 100-pin TQFP, 119-ball PBGA, and 165-
ball PBGA packages
• Power supply:
NVF: V
dd
2.5V (± 5%), V
ddq
2.5V (± 5%)
NLF: V
dd
3.3V (± 5%), V
ddq
3.3V/2.5V (± 5%)
• JTAG Boundary Scan for PBGA packages
• Industrial temperature available
• Lead-free available
FAST ACCESS TIME
Symbol 
t
kq
t
kc
Parameter 
Clock Access Time
Cycle Time
Frequency
6.5 
6.5
7.5
133
7.5 
7.5
8.5
117
Units
ns
ns
MHz
Copyright © 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev.  F
08/11/2011
1
 
IS61NLF25636A/IS61NVF25636A
IS61NLF51218A/IS61NVF51218A   
BLOCK DIAGRAM
x 36: A [0:17] or
x 18: A [0:18]
ADDRESS
REGISTER
A2-A17 or A2-A18
256Kx36;
512Kx18
MEMORY ARRAY
MODE
A0-A1
BURST
ADDRESS
COUNTER
A'0-A'1
K
DATA-IN
REGISTER
CLK
CKE
CONTROL
LOGIC
K
WRITE
ADDRESS
REGISTER
WRITE
ADDRESS
REGISTER
K
DATA-IN
REGISTER
CE
CE2
CE2
ADV
WE
BWŸ
X
OE
ZZ
DQx/DQPx
}
CONTROL
REGISTER
CONTROL
LOGIC
K
(X= a-d, or a,b)
BUFFER
36 or 18
2
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev.  F
08/11/2011
 
IS61NLF25636A/IS61NVF25636A
IS61NLF51218A/IS61NVF51218A   
165-Ball, 13 mm x 15mm BGA
Bottom View
119-Ball, 14 mm x 22 mm BGA
Bottom View
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev.  F 
08/11/2011
3
 
IS61NLF25636A/IS61NVF25636A
IS61NLF51218A/IS61NVF51218A   
PIN CONFIGURATION    256K 
x
 36, 165-Ball PBGA (TOP VIEW) 
—
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
1
NC
NC
DQPc
DQc
DQc
DQc
DQc
NC
DQd
DQd
DQd
DQd
DQPd
NC
MODE
2
A
A
NC
DQc
DQc
DQc
DQc
NC
DQd
DQd
DQd
DQd
NC
NC
NC
3
CE
CE2
V
ddq
V
ddq
V
ddq
V
ddq
V
ddq
NC
V
ddq
V
ddq
V
ddq
V
ddq
V
ddq
A
A
4
BWc
BWd
V
SS
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
SS
A
A
5
BWb
BWa
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TdI
TMS
6
CE2
CLK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A1*
A0*
7
CKE
WE
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCK
8
ADV
OE
V
SS
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
SS
A
A
9
A
NC
V
ddq
V
ddq
V
ddq
V
ddq
V
ddq
NC
V
ddq
V
ddq
V
ddq
V
ddq
V
ddq
A
A
10
A
A
NC
DQb
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQa
NC
A
A
11
NC
NC
DQPb
DQb
DQb
DQb
DQb
ZZ
DQa
DQa
DQa
DQa
DQPa
NC
A
Note:
A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
A0, A1
ADV
Pin Name
Address Inputs
Synchronous Burst Address Inputs
Synchronous Burst Address Advance/
Load
WE
Synchronous Read/Write Control
Input
CLK
Synchronous Clock
CKE
Clock Enable
CE, CE2, CE2
Synchronous Chip Enable
BWx (x=a-d)
Synchronous Byte Write Inputs
OE
Output Enable
ZZ
Power Sleep Mode
MODE
TCK, TDI
TDO, TMS
V
DD
NC
DQx
DQPx
V
DDQ
V
SS
Burst Sequence Selection
JTAG Pins
3.3V/2.5V Power Supply
No Connect
Data Inputs/Outputs
Parity Data I/O
Isolated output Power Supply
3.3V/2.5V
Ground
4
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev.  F
08/11/2011
 
IS61NLF25636A/IS61NVF25636A
IS61NLF51218A/IS61NVF51218A   
119-PIN PBGA PACKAGE CONFIGURATION       256K x 36 (TOP VIEW) 
1
2
3
4
5
6
7
A
B
C
D
E
F
V
DDQ
NC
NC
DQc
DQc
V
DDQ
DQc
DQc
V
DDQ
DQd
DQd
V
DDQ
DQd
DQd
NC
NC
V
DDQ
A
CE2
A
DQPc
DQc
DQc
DQc
DQc
V
DD
DQd
DQd
DQd
DQd
DQPd
A
NC
TMS
A
A
A
V
SS
V
SS
V
SS
BWc
V
SS
NC
V
SS
BWd
V
SS
V
SS
V
SS
MODE
A
TDI
NC
ADV
V
DD
NC
CE
OE
A
WE
V
DD
CLK
NC
CKE
A
1
*
A
0
*
V
DD
A
TCK
A
A
A
Vss
Vss
Vss
BWb
Vss
NC
Vss
BWa
Vss
Vss
Vss
NC
A
TDO
A
CE2
A
DQPb
DQb
DQb
DQb
DQb
V
DD
DQa
DQa
DQa
DQa
DQPa
A
NC
NC
V
DDQ
NC
NC
DQb
DQb
V
DDQ
DQb
DQb
V
DDQ
DQa
DQa
V
DDQ
DQa
DQa
NC
ZZ
V
DDQ
G
H
J
K
L
M
N
P
R
T
U
Note:
A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
A0, A1
ADV
WE
CLK
CKE
CE
CE2
CE2
BWx (x=a-d)
Pin Name
Address Inputs
Synchronous Burst Address Inputs
Synchronous Burst Address Advance/
Load
Synchronous Read/Write Control
Input
Synchronous Clock
Clock Enable
Synchronous Chip Select
Synchronous Chip Select
Synchronous Chip Select
Synchronous Byte Write Inputs
OE
ZZ
MODE
TCK, TDO
TMS, TDI
V
dd
V
SS
NC
DQa-DQd
DQPa-Pd
V
ddq
Output Enable
Power Sleep Mode
Burst Sequence Selection
JTAG Pins
Power Supply
Ground
No Connect
Data Inputs/Outputs
Parity Data I/O
Output Power Supply
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev.  F 
08/11/2011
5
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器件捷径:
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ
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