liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
09/10/07
1
IS61NLP12832B
IS61NLP12836B/IS61NVP12836B
IS61NLP25618A/IS61NVP25618A
BLOCK DIAGRAM
x 32/x 36: A [0:16] or
x 18: A [0:17]
ADDRESS
REGISTER
A2-A16 or A2-A17
128Kx32;
128Kx36;
256Kx18
MEMORY ARRAY
K
DATA-IN
REGISTER
MODE
A0-A1
BURST
ADDRESS
COUNTER
A'0-A'1
CLK
CKE
CONTROL
LOGIC
K
WRITE
ADDRESS
REGISTER
WRITE
ADDRESS
REGISTER
K
DATA-IN
REGISTER
CE
CE2
CE2
ADV
WE
BWŸ
X
OE
ZZ
DQx/DQPx
}
CONTROL
REGISTER
CONTROL
LOGIC
K
OUTPUT
REGISTER
BUFFER
(X=a,b,c,d or a,b)
32, 36 or 18
2
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
09/10/07
IS61NLP12832B
IS61NLP12836B/IS61NVP12836B
IS61NLP25618A/IS61NVP25618A
165-Ball, 13 mm x 15mm BGA
1 mm Ball Pitch, 11 x 15 Ball Array
Bottom View
119-Ball, 14 mm x 22 mm BGA
1 mm Ball Pitch, 7 x 17 Ball Array
Bottom View
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
09/10/07
3
IS61NLP12832B
IS61NLP12836B/IS61NVP12836B
IS61NLP25618A/IS61NVP25618A
PIN CONFIgURATION — 128K
x
36, 165-Ball PBgA (TOP VIEW)
1
2
3
4
5
6
7
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC
NC
DQPc
DQc
DQc
DQc
DQc
NC
DQd
DQd
DQd
DQd
DQPd
NC
MODE
A
A
NC
DQc
DQc
DQc
DQc
NC
DQd
DQd
DQd
DQd
NC
NC
NC
CE
CE2
V
ddq
V
ddq
V
ddq
V
ddq
V
ddq
NC
V
ddq
V
ddq
V
ddq
V
ddq
V
ddq
A
A
BWc
BWd
V
SS
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
SS
A
A
BWb
BWa
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
NC
NC
CE2
CLK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A1*
A0*
CKE
WE
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
NC
NC
8
9
NC
NC
V
ddq
V
ddq
V
ddq
V
ddq
V
ddq
NC
V
ddq
V
ddq
V
ddq
V
ddq
V
ddq
A
A
10
A
A
NC
DQb
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQa
NC
A
A
11
NC
NC
DQPb
DQb
DQb
DQb
DQb
ZZ
DQa
DQa
DQa
DQa
DQPa
NC
A
ADV
OE
V
SS
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
SS
A
A
Note:
A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
A0, A1
ADV
Pin Name
Address Inputs
Synchronous Burst Address Inputs
Synchronous Burst Address Advance/
Load
WE
Synchronous Read/Write Control
Input
CLK
Synchronous Clock
CKE
Clock Enable
CE, CE2,
CE2 Synchronous Chip Enable
BWx (x=a-d)
Synchronous Byte Write Inputs
OE
Output Enable
ZZ
Power Sleep Mode
MODE
V
DD
NC
DQx
DQPx
V
DDQ
V
SS
Burst Sequence Selection
3.3V/2.5V Power Supply
No Connect
Data Inputs/Outputs
Parity Data I/O
Isolated output Power Supply
3.3V/2.5V
Ground
4
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
09/10/07
IS61NLP12832B
IS61NLP12836B/IS61NVP12836B
IS61NLP25618A/IS61NVP25618A
119-PIN
PBgA PACKAgE
CONFIGURATION
1
2
3
128K x 36 (TOP VIEW)
4
5
6
7
A
B
C
D
E
F
V
DDQ
NC
NC
DQc
DQc
V
DDQ
DQc
DQc
V
DDQ
DQd
DQd
V
DDQ
DQd
DQd
NC
NC
V
DDQ
A
CE2
A
DQPc
DQc
DQc
DQc
DQc
V
DD
DQd
DQd
DQd
DQd
DQPd
A
NC
NC
A
A
A
V
SS
V
SS
V
SS
BWc
V
SS
NC
V
SS
BWd
V
SS
V
SS
V
SS
MODE
A
NC
NC
ADV
V
DD
NC
CE
OE
NC
WE
V
DD
CLK
NC
CKE
A
1
*
A
0
*
V
DD
A
NC
A
A
A
Vss
Vss
Vss
BWb
Vss
NC
Vss
BWa
Vss
Vss
Vss
NC
A
NC
A
CE2
A
DQPb
DQb
DQb
DQb
DQb
V
DD
DQa
DQa
DQa
DQa
DQPa
A
NC
NC
V
DDQ
NC
NC
DQb
DQb
V
DDQ
DQb
DQb
V
DDQ
DQa
DQa
V
DDQ
DQa
DQa
NC
ZZ
V
DDQ
G
H
J
K
L
M
N
P
R
T
U
Note:
A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
使用J-LINK仿真器下载HEX文件到STM32芯片 工具/原料 J-Flash ARM 开发板 J-LINK仿真器 方法/步骤 打开“开始”-“所有程序”-SEGGER-JLink ARM v4.14c-J Flash ARM 打开“Option”选择“Project settings…”，进行烧写前的必要设置，如下图： ...[详细]
单片机
