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IS61NLP51236-200B3-TR

sram 18mb 512kx36 200mhz sync sram 3.3v

器件类别：半导体    其他集成电路（IC）   

厂商名称：All Sensors

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器件参数
参数名称
属性值
Manufacture
ISSI
产品种类
Product Category
SRAM
RoHS
N
Memory Size
18 Mbi
Organizati
512 k x 36
Access Time
3.1 ns
Interface
Parallel
电源电压-最大
Supply Voltage - Max
3.465 V
Supply Voltage - Mi
3.135 V
Maximum Operating Curre
425 mA
最大工作温度
Maximum Operating Temperature
+ 70 C
最小工作温度
Minimum Operating Temperature
0 C
安装风格
Mounting Style
SMD/SMT
封装 / 箱体
Package / Case
PBGA-165
系列
Packaging
Reel
Maximum Clock Frequency
200 MHz
工厂包装数量
Factory Pack Quantity
2000
类型
Type
Synchronous
文档预览
IS61NLP25672/IS61NVP25672
IS61NLP51236/IS61NVP51236
IS61NLP102418/IS61NVP102418 
 
256K x 72, 512K x 36 and 1M x 18
18Mb, PIPELINE 'NO WAIT' STATE BUS SRAM
SEPTEMBER 2011
FEATURES
• 100 percent bus utilization
• No wait cycles between Read and Write
• Internal self-timed write cycle
• Individual Byte Write Control
• Single R/W (Read/Write) control pin
• Clock controlled, registered address,
data and control
DESCRIPTION
The 18 Meg 'NLP/NVP' product family feature high-speed,
low-power synchronous static RAMs designed to provide
a burstable, high-performance, 'no wait' state, device
for networking and communications applications. They
are organized as 256K words by 72 bits, 512K words
by 36 bits and 1M words by 18 bits, fabricated with
ISSI
's
advanced CMOS technology.
Incorporating a 'no wait' state feature, wait cycles are
eliminated when the bus switches from read to write, or
write to read. This device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs
into a single monolithic circuit.
All synchronous inputs pass through registers are controlled
by a positive-edge-triggered single clock input. Operations
may be suspended and all synchronous inputs ignored
when Clock Enable, CKE is HIGH. In this state the internal
device will hold their previous values.
All Read, Write and Deselect cycles are initiated by the ADV
input. When the ADV is HIGH the internal burst counter
is incremented. New external addresses can be loaded
when ADV is LOW.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock inputs and when WE is LOW.
Separate byte enables allow individual bytes to be written.
A burst mode pin (MODE) defines the order of the burst
sequence. When tied HIGH, the interleaved burst sequence
is selected. When tied LOW, the linear burst sequence is
selected.
• Interleaved or linear burst sequence control us-
ing MODE input
• Three chip enables for simple depth expansion
and address pipelining
• Power Down mode
• Common data inputs and data outputs
•
CKE pin to enable clock and suspend operation
• JEDEC 100-pin TQFP, 119-ball PBGA, 165-ball
PBGA and 209-ball (x72) PBGA packages
• Power supply:
NVP: V
dd
2.5V (± 5%), V
ddq
2.5V (± 5%)
NLP: V
dd
3.3V (± 5%), V
ddq
3.3V/2.5V (± 5%)
• JTAG Boundary Scan for PBGA packages
• Industrial temperature available
• Lead-free available
• Leaded option available upon request
FAST ACCESS TIME
Symbol 
t
kq
t
kc
Parameter 
Clock Access Time
Cycle Time
Frequency
-250 
2.6
4
250
-200 
3.1
5
200
Units
ns
ns
MHz
Copyright © 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com
Rev.  O
09/19/2011
1
IS61NLP25672/IS61NVP25672 
IS61NLP51236/IS61NVP51236
IS61NLP102418/IS61NVP102418   
BLOCK DIAGRAM
x 72: A [0:17] or
x 36: A [0:18] or
x 18: A [0:19]
ADDRESS
REGISTER
A2-A17 or A2-A18 or A2-A19
256Kx72; 512Kx36;
1024Kx18
MEMORY ARRAY
MODE
A0-A1
BURST
ADDRESS
COUNTER
A'0-A'1
K
DATA-IN
REGISTER
CLK
CKE
CONTROL
LOGIC
K
WRITE
ADDRESS
REGISTER
WRITE
ADDRESS
REGISTER
K
DATA-IN
REGISTER
CE
CE2
CE2
ADV
WE
BWŸ
X
OE
ZZ
DQx/DQPx
}
CONTROL
REGISTER
CONTROL
LOGIC
K
OUTPUT
REGISTER
BUFFER
(X=a,b,c,d or a,b)
72, 36 or 18
2
Integrated Silicon Solution, Inc. — www.issi.com
Rev.  O
09/19/2011
IS61NLP25672/IS61NVP25672 
IS61NLP51236/IS61NVP51236
IS61NLP102418/IS61NVP102418   
165-Ball, 13 mm x 15mm BGA
1 mm Ball Pitch, 11 x 15 Ball Array
Bottom View
209-Ball, 14 mm x 22 mm BGA
1 mm Ball Pitch, 11 x 19 Ball Array
Bottom View
Integrated Silicon Solution, Inc. — www.issi.com
Rev.  O
09/19/2011
3
IS61NLP25672/IS61NVP25672 
IS61NLP51236/IS61NVP51236
IS61NLP102418/IS61NVP102418   
PIN CONFIgURATION    256K x 72, 209-Ball PBgA (TOP VIEW)
—
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
1
DQg
DQg
DQg
DQg
DQPg
DQc
DQc
DQc
DQc
NC
DQh
DQh
DQh
DQh
DQPd
DQd
DQd
DQd
DQd
2
DQg
DQg
DQg
DQg
DQPc
DQc
DQc
DQc
DQc
NC
DQh
DQh
DQh
DQh
DQPh
DQd
DQd
DQd
DQd
3
A
BWc
BWh
V
SS
V
ddq
V
SS
V
ddq
V
SS
V
ddq
CLK
V
ddq
V
SS
V
ddq
V
SS
V
ddq
V
SS
NC
A
TMS
4
CE2
BWg
BWd
NC
V
ddq
V
SS
V
ddq
V
SS
V
ddq
NC
V
ddq
V
SS
V
ddq
V
SS
V
ddq
NC
A
A
TDI
5
A
NC
NC
NC
V
dd
V
SS
V
dd
V
SS
V
dd
V
SS
V
dd
V
SS
V
dd
V
SS
V
dd
NC
NC
A
A
6
ADV
WE
CE
OE
V
dd
NC
NC
NC
NC
CKE
NC
NC
NC
ZZ
V
dd
MODE
A
A1
A0
7
A
A
NC
NC
V
dd
V
SS
V
dd
V
SS
V
dd
V
SS
V
dd
V
SS
V
dd
V
SS
V
dd
NC
NC
A
A
8
CE2
BWb
BWe
NC
V
ddq
V
SS
V
ddq
V
SS
V
ddq
NC
V
ddq
V
SS
V
ddq
V
SS
V
ddq
NC
A
A
TDO
9
A
BWf
BWa
V
SS
V
ddq
V
SS
V
ddq
V
SS
V
ddq
NC
V
ddq
V
SS
V
ddq
V
SS
V
ddq
V
SS
NC
A
TCK
10
DQb
DQb
DQb
DQb
DQPf
DQf
DQf
DQf
DQf
NC
DQa
DQa
DQa
DQa
DQPa
DQe
DQe
DQe
DQe
11
DQb
DQb
DQb
DQb
DQPb
DQf
DQf
DQf
DQf
NC
DQa
DQa
DQa
DQa
DQPe
DQe
DQe
DQe
DQe
11 x 19 Ball BGA—14 x 22 mm
2
Body—1 mm Ball Pitch
PIN DESCRIPTIONS
Symbol
A
A0, A1
Pin Name
Synchronous Address Inputs
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
ADV
Synchronous Burst Address Advance
BWa-BWh
Synchronous Byte Write Enable
CE, CE2, CE2
Synchronous Chip Enable
CLK
Synchronous Clock
CKE
Clock Enable
DQx
Synchronous Data Input/Output
DQPx
Parity Data I/O
V
SS
MODE
OE
TCK, TDI
TDO, TMS
V
dd
V
ddq
WE
ZZ
Ground
Burst Sequence Selection
Output Enable
JTAG Pins
3.3V/2.5V Power Supply
Isolated Output Buffer Supply:
3.3V/2.5V
Write Enable
Snooze Enable
4
Integrated Silicon Solution, Inc. — www.issi.com
Rev.  O
09/19/2011
IS61NLP25672/IS61NVP25672 
IS61NLP51236/IS61NVP51236
IS61NLP102418/IS61NVP102418   
PIN CONFIgURATION    512K 
x
 36, 165-Ball PBgA (TOP VIEW) 
—
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC
NC
DQPc
DQc
DQc
DQc
DQc
NC
DQd
DQd
DQd
DQd
DQPd
NC
MODE
2
A
A
NC
DQc
DQc
DQc
DQc
VDD
DQd
DQd
DQd
DQd
NC
NC
NC
3
CE
CE2
V
ddq
V
ddq
V
ddq
V
ddq
V
ddq
NC
V
ddq
V
ddq
V
ddq
V
ddq
V
ddq
A
A
4
BWc
BWd
V
SS
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
SS
A
A
5
BWb
BWa
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TdI
TMS
6
CE2
CLK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A1*
A0*
7
CKE
WE
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCK
8
ADV
OE
V
SS
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
SS
A
A
9
A
A
V
ddq
V
ddq
V
ddq
V
ddq
V
ddq
NC
V
ddq
V
ddq
V
ddq
V
ddq
V
ddq
A
A
10
A
A
NC
DQb
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQa
NC
A
A
11
NC
NC
DQPb
DQb
DQb
DQb
DQb
ZZ
DQa
DQa
DQa
DQa
DQPa
NC
A
Note:
A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
A0, A1
ADV
Pin Name
Address Inputs
Synchronous Burst Address Inputs
Synchronous Burst Address Advance/
Load
WE
Synchronous Read/Write Control
Input
CLK
Synchronous Clock
CKE
Clock Enable
CE, CE2, CE2
Synchronous Chip Enable
BWx (x=a-d)
Synchronous Byte Write Inputs
OE
Output Enable
ZZ
Power Sleep Mode
MODE
TCK, TDI
TDO, TMS
V
DD
NC
DQx
DQPx
V
DDQ
V
SS
Burst Sequence Selection
JTAG Pins
3.3V/2.5V Power Supply
No Connect
Data Inputs/Outputs
Parity Data I/O
Isolated output Power Supply
3.3V/2.5V
Ground
Integrated Silicon Solution, Inc. — www.issi.com
Rev.  O
09/19/2011
5
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参数对比
与IS61NLP51236-200B3-TR相近的元器件有：IS61NLP25672-200B1-TR、IS61NLP102418-200TQ-TR、IS61NVP51236-200B3I-TR、IS61NLP102418-250B3-TR、IS61NLP102418-250B3、IS61NVP51236-200B3I、IS61NLP51236-200B3、IS61NLP102418-200TQ、IS61NLP25672-200B1。描述及对比如下：
型号 IS61NLP51236-200B3-TR IS61NLP25672-200B1-TR IS61NLP102418-200TQ-TR IS61NVP51236-200B3I-TR IS61NLP102418-250B3-TR IS61NLP102418-250B3 IS61NVP51236-200B3I IS61NLP51236-200B3 IS61NLP102418-200TQ IS61NLP25672-200B1
描述 sram 18mb 512kx36 200mhz sync sram 3.3v sram 18mb 256kx72 200mhz sync sram 3.3v sram 18mb 1mbx18 200mhz sync sram 3.3v sram 18mb 512kx36 sync sram 2.5v sram 18mb 1mbx18 250mhz sync sram 3.3v sram 18mb 1mbx18 250mhz sync sram 3.3v sram 18mb 512kx36 sync sram 2.5v sram 18mb 512kx36 200mhz sync sram 3.3v sram 18mb 1mbx18 200mhz sync sram 3.3v sram 18mb 256kx72 200mhz sync sram 3.3v
Manufacture ISSI ISSI ISSI ISSI ISSI ISSI ISSI ISSI ISSI ISSI
产品种类
Product Category		 SRAM SRAM SRAM SRAM SRAM SRAM SRAM SRAM SRAM SRAM
RoHS N N N N N N N N N N
Memory Size 18 Mbi 18 Mbi 18 Mbi 18 Mbi 18 Mbi 18 Mbi 18 Mbi 18 Mbi 18 Mbi 18 Mbi
Organizati 512 k x 36 256 k x 72 1 M x 18 512 k x 36 1 M x 18 1 M x 18 512 k x 36 512 k x 36 1 M x 18 256 k x 72
Access Time 3.1 ns 3.1 ns 3.1 ns 3.1 ns 2.6 ns 2.6 ns 3.1 ns 3.1 ns 3.1 ns 3.1 ns
Interface Parallel Parallel Parallel Parallel Parallel Parallel Parallel Parallel Parallel Parallel
电源电压-最大
Supply Voltage - Max		 3.465 V 3.465 V 3.465 V 2.625 V 3.465 V 3.465 V 2.625 V 3.465 V 3.465 V 3.465 V
Supply Voltage - Mi 3.135 V 3.135 V 3.135 V 2.375 V 3.135 V 3.135 V 2.375 V 3.135 V 3.135 V 3.135 V
Maximum Operating Curre 425 mA 550 mA 425 mA 475 mA 450 mA 450 mA 475 mA 425 mA 425 mA 550 mA
最大工作温度
Maximum Operating Temperature		 + 70 C + 70 C + 70 C + 85 C + 70 C + 70 C + 85 C + 70 C + 70 C + 70 C
最小工作温度
Minimum Operating Temperature		 0 C 0 C 0 C - 40 C 0 C 0 C - 40 C 0 C 0 C 0 C
安装风格
Mounting Style		 SMD/SMT SMD/SMT SMD/SMT SMD/SMT SMD/SMT SMD/SMT SMD/SMT SMD/SMT SMD/SMT SMD/SMT
封装 / 箱体
Package / Case		 PBGA-165 PBGA-209 TQFP-100 PBGA-165 PBGA-165 PBGA-165 PBGA-165 PBGA-165 TQFP-100 PBGA-209
系列
Packaging		 Reel Reel Reel Reel Reel Tray Tray Tray Tube Tube
Maximum Clock Frequency 200 MHz 200 MHz 200 MHz 200 MHz 250 MHz 250 MHz 200 MHz 200 MHz 200 MHz 200 MHz
工厂包装数量
Factory Pack Quantity		 2000 1000 800 2000 2000 144 144 144 72 84
类型
Type		 Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous
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器件捷径:
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ
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