liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00C
02/20/2013
1
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
BLOCK DIAGRAM
A0-20 ( A0-21)
A0-20(A0-21)
Address
Registers
MODE
ADV
A0-A1
K
CLK
Address
Registers
Burst Logic
K
A'0-A'1
A2-20(A2-A21)
A0-20 ( A0-21)
2Mx36;
4Mx18
Memory Array
Address
Registers
/CKE
Data-In
Register
K
Control register
/CE
CE2
/CE2
ADV
/WE
/BWx
(X=a,b,c,d or a,b)
Data-In
Register
Control Logic
K
/OE
ZZ
36(18)
DQx/DQPx
K
Output
Buffers
2
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00C
02/20/2013
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
165-PIN BGA
165-Ball, 13x15 mm BGA
165-Ball, 15x17 mm BGA
1mm Ball Pitch, 11x15 Ball Array
119-PIN BGA
119-Ball, 14x22 mm BGA
1.27mm Ball Pitch, 7x17 Ball Array
BOTTOM VIEW
BOTTOM VIEW
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00C
02/20/2013
3
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
PIN CONFIGURATION — 2M
x
36, 165-Ball PBGA (TOP VIEW)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC
NC
DQPc
DQc
DQc
DQc
DQc
NC
DQd
DQd
DQd
DQd
DQPd
NC
MODE
2
A
A
NC
DQc
DQc
DQc
DQc
NC
DQd
DQd
DQd
DQd
NC
A
A
3
CE
CE2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
A
4
BWc
BWd
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
A
5
BWb
BWa
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDI
TMS
6
CE2
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
A1*
A0*
7
CKE
WE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDO
TCK
8
ADV
OE
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
A
9
A
A
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
A
10
A
A
NC
DQb
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQa
NC
A
A
11
NC
NC
DQPb
DQb
DQb
DQb
DQb
ZZ
DQa
DQa
DQa
DQa
DQPa
NC
A
Note:
A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
A0, A1
ADV
Pin Name
Synchronous Address Inputs
Synchronous Burst Address Inputs
Synchronous Burst Address Advance/
Load
WE
Synchronous Read/Write Control Input
CLK
Synchronous Clock
CKE
Synchronous Clock Enable
CE, CE2,
CE2 Synchronous Chip Enable
BWa-BWd
Synchronous Byte Write Inputs
OE
Asynchronous Output Enable
ZZ
Asynchronous Power Sleep
Mode
MODE
TCK, TDI
TDO, TMS
V
DD
NC
DQa-DQd
DQPa-DQPd
V
DDQ
V
ss
Burst Sequence Selection
JTAG Pins
Power Supply
No Connect
Synchronous Data Inputs/Outputs
Synchronous Parity Data
Inputs/Outputs
I/O Power Supply
Ground
4
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00C
02/20/2013
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
119-PIN
PBGA PACKAGE
CONFIGURATION
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
VDDQ
NC
NC
DQc
DQc
VDDQ
DQc
DQc
VDDQ
DQd
DQd
VDDQ
DQd
DQd
NC
NC
VDDQ
2
A
CE2
A
DQPc
DQc
DQc
DQc
DQc
VDD
DQd
DQd
DQd
DQd
DQPd
A
A
TMS
3
A
A
A
VSS
VSS
VSS
BWc
VSS
NC
VSS
BWd
VSS
VSS
VSS
MODE
A
TDI
4
A
ADV
VDD
NC
CE
OE
A
WE
VDD
CLK
NC
CKE
A1*
A0*
VDD
A
TCK
2M x 36 (TOP VIEW)
5
A
A
A
VSS
VSS
VSS
BWb
VSS
NC
VSS
BWa
VSS
VSS
VSS
NC
A
TDO
6
A
CE2
A
DQPb
DQb
DQb
DQb
DQb
VDD
DQa
DQa
DQa
DQa
DQPa
A
A
NC
7
VDDQ
NC
NC
DQb
DQb
VDDQ
DQb
DQb
VDDQ
DQa
DQa
VDDQ
DQa
DQa
NC
ZZ
VDDQ
Note:
A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
