IS61(4)NLP12836EC/IS61(4)NVP12836EC/IS61(4)NLP12832EC
IS61(4)NVP12832EC/IS61(4)NLP25618EC/IS61(4)NVP25618EC
128K x36/32 and 256K x18 4Mb, ECC, PIPELINE 'NO WAIT' STATE
BUS SYNCHRONOUS SRAM
MAY 2013
FEATURES
•
100 percent bus utilization
•
No wait cycles between Read and Write
•
Internal self-timed write cycle
•
Individual Byte Write Control
•
Single R/W (Read/Write) control pin
•
Clock controlled, registered address, data and
control
•
Interleaved or linear burst sequence control
using MODE input
•
Three chip enables for simple depth
expansion and address pipelining
•
Power Down mode
•
Common data inputs and data outputs
•
/CKE pin to enable clock and suspend
operation
•
JEDEC 100-pin TQFP, 165-ball PBGA and
119-ball PBGA packages
•
Power supply:
NLP: V
DD
3.3V (± 5%), V
DDQ
3.3V/2.5V (± 5%)
NVP: V
DD
2.5V (± 5%), V
DDQ
2.5V (± 5%)
•
JTAG Boundary Scan for PBGA packages
•
Industrial and Automotive temperature support
•
Lead-free available
•
Error Detection and Error Correction
DESCRIPTION
The 4Mb product family features high-speed, low-
power synchronous static RAMs designed to
provide a burstable, high-performance, 'no wait'
state, device for networking and communications
applications. They are organized as 128K words
by 36 bits and 256K words by 18 bits, fabricated
with
ISSI's
advanced CMOS technology.
Incorporating a 'no wait' state feature, wait cycles
are eliminated when the bus switches from read
to write, or write to read. This device integrates a
2-bit burst counter, high-speed SRAM core, and
high-drive capability outputs into a single
monolithic circuit.
All synchronous inputs pass through registers are
controlled by a positive-edge-triggered single
clock input. Operations may be suspended and all
synchronous inputs ignored when Clock Enable,
/CKE is HIGH. In this state the internal device will
hold their previous values.
All Read, Write and Deselect cycles are initiated
by the ADV input. When the ADV is HIGH the
internal burst counter is incremented. New
external addresses can be loaded when ADV is
LOW.
Write cycles are internally self-timed and are
initiated by the rising edge of the clock inputs and
when /WE is LOW. Separate byte enables allow
individual bytes to be written.
A burst mode pin (MODE) defines the order of the
burst sequence. When tied HIGH, the interleaved
burst sequence is selected. When tied LOW, the
linear burst sequence is selected
250
2.6
4
250
200
3.1
5
200
Units
ns
ns
MHz
FAST ACCESS TIME
Symbol
t
KQ
t
KC
f
MAX
Parameter
Clock Access Time
Cycle time
Frequency
Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
05/03/2013
1
IS61(4)NLP12836EC/IS61(4)NVP12836EC/IS61(4)NLP12832EC
IS61(4)NVP12832EC/IS61(4)NLP25618EC/IS61(4)NVP25618EC
BLOCK DIAGRAM
A0-16 ( A0-17)
A2-16(A2-A17)
A0-16(A0-17)
Address
Registers
MODE
ADV
A0-A1
K
K
Address
Registers
Address
Registers
Burst Logic
A'0-A'1
128Kx32;
128Kx36;
256Kx18
Memory Array
ECC
Array
A0-16 ( A0-17)
CLK
ECC Logic
ECC Logic
/CKE
Data-In
Register
/CE
CE2
/CE2
ADV
/WE
/BWx
(X=a,b,c,d or a,b)
K
Control register
Data-In
Register
Control Logic
K
/OE
ZZ
36, 18 (32)
DQx/DQPx
K
Output
Buffers
Output
tput
Register
K
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
05/03/2013
2
IS61(4)NLP12836EC/IS61(4)NVP12836EC/IS61(4)NLP12832EC
IS61(4)NVP12832EC/IS61(4)NLP25618EC/IS61(4)NVP25618EC
PIN CONFIGURATION
128K x 36, 165-Ball PBGA (Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
2
3
4
5
6
7
8
9
10
11
NC
NC
DQPc
DQc
DQc
DQc
DQc
NC
DQd
DQd
DQd
DQd
DQPd
NC
MODE
A
A
NC
DQc
DQc
DQc
DQc
NC
DQd
DQd
DQd
DQd
NC
NC
NC
/CE
CE2
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
/BWc
/BWd
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
/BWb
/BWa
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
/CE2
CLK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A1*
A0*
/CKE
/WE
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCK
ADV
/OE
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
NC
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
A
A
NC
DQb
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQa
NC
A
A
NC
NC
DQPb
DQb
DQb
DQb
DQb
ZZ
DQa
DQa
DQa
DQa
DQPa
NC
A
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
CLK
/CKE
A0,A1
A
/ADV
/CE,CE2,/CE2
/BWE
/BWx (x=a-d)
/OE
DQx
DQPx
MODE
ZZ
TCK,TDI,TDO,TMS
VDD
VDDQ
Pin Name
Synchronous Clock
Clock Enable
Synchronous Burst Address Inputs
Synchronous Address Inputs
Synchronous Advance/Load
Synchronous Chip Enable
Synchronous Byte Write Enable
Synchronous Byte Write Inputs
Asynchronous Output Enable
Synchronous Data Inputs/Outputs
Synchronous Parity Data I/O
Burst Sequence Selection
Asynchronous Power Sleep Mode
JTAG Pins
Power Supply
I/O Power Supply
Ground
No Connect
Bottom View
165-Ball, 13 mm x 15mm BGA
1 mm Ball Pitch, 11 x 15 Ball Array
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
05/03/2013
VSS
NC
3
IS61(4)NLP12836EC/IS61(4)NVP12836EC/IS61(4)NLP12832EC
IS61(4)NVP12832EC/IS61(4)NLP25618EC/IS61(4)NVP25618EC
128K x 32, 165-Ball PBGA (Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
2
3
4
5
6
7
8
9
10
11
NC
NC
NC
DQc
DQc
DQc
DQc
NC
DQd
DQd
DQd
DQd
NC
NC
MODE
A
A
NC
DQc
DQc
DQc
DQc
NC
DQd
DQd
DQd
DQd
NC
NC
NC
/CE
CE2
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
/BWc
/BWd
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
/BWb
/BWa
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
/CE2
CLK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A1*
A0*
/CKE
/WE
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCK
ADV
/OE
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
NC
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
A
A
NC
DQb
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQa
NC
A
A
NC
NC
NC
DQb
DQb
DQb
DQb
ZZ
DQa
DQa
DQa
DQa
NC
NC
A
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
CLK
/CKE
A0,A1
A
/ADV
/CE,CE2,/CE2
/BWE
/BWx (x=a-d)
/OE
DQx
MODE
ZZ
TCK,TDI,TDO,TMS
VDD
VDDQ
VSS
NC
Pin Name
Synchronous Clock
Clock Enable
Synchronous Burst Address Inputs
Synchronous Address Inputs
Synchronous Advance/Load
Synchronous Chip Enable
Synchronous Byte Write Enable
Synchronous Byte Write Inputs
Asynchronous Output Enable
Synchronous Data Inputs/Outputs
Burst Sequence Selection
Asynchronous Power Sleep Mode
JTAG Pins
Power Supply
I/O Power Supply
Ground
No Connect
Bottom View
165-Ball, 13 mm x 15mm BGA
1 mm Ball Pitch, 11 x 15 Ball Array
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
05/03/2013
4
IS61(4)NLP12836EC/IS61(4)NVP12836EC/IS61(4)NLP12832EC
IS61(4)NVP12832EC/IS61(4)NLP25618EC/IS61(4)NVP25618EC
256K x 18, 165-Ball PBGA (Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
2
3
4
5
6
7
8
9
10
11
NC
NC
NC
NC
NC
NC
NC
NC
DQb
DQb
DQb
DQb
DQPb
NC
MODE
A
A
NC
DQb
DQb
DQb
DQb
NC
NC
NC
NC
NC
NC
NC
NC
/CE
CE2
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
/BWb
NC
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
NC
/BWa
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
/CE2
CLK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A1*
A0*
/CKE
/WE
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCK
ADV
/OE
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
NC
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
A
A
NC
NC
NC
NC
NC
NC
DQa
DQa
DQa
DQa
NC
A
A
A
NC
DQPa
DQa
DQa
DQa
DQa
ZZ
NC
NC
NC
NC
NC
NC
A
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
CLK
/CKE
A0,A1
A
/ADV
/CE,CE2,/CE2
/BWE
/BWx (x=a-b)
/OE
DQx
DQPx
MODE
ZZ
TCK,TDI,TDO,TMS
VDD
VDDQ
VSS
NC
Pin Name
Synchronous Clock
Clock Enable
Synchronous Burst Address Inputs
Synchronous Address Inputs
Synchronous Advance/Load
Synchronous Chip Enable
Synchronous Byte Write Enable
Synchronous Byte Write Inputs
Asynchronous Output Enable
Synchronous Data Inputs/Outputs
Synchronous Parity Data I/O
Burst Sequence Selection
Asynchronous Power Sleep Mode
JTAG Pins
Power Supply
I/O Power Supply
Ground
No Connect
Bottom View
165-Ball, 13 mm x 15mm BGA
1 mm Ball Pitch, 11 x 15 Ball Array
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
05/03/2013
5
微控制器 MCU
