liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. J
08/25/2014
1
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A
BLOCK DIAGRAM
x 36: A [0:17] or
x 18: A [0:18]
ADDRESS
REGISTER
A2-A17 or A2-A18
256Kx36;
512Kx18
MEMORY ARRAY
MODE
A0-A1
BURST
ADDRESS
COUNTER
A'0-A'1
K
DATA-IN
REGISTER
CLK
CKE
CONTROL
LOGIC
K
WRITE
ADDRESS
REGISTER
WRITE
ADDRESS
REGISTER
K
DATA-IN
REGISTER
CE
CE2
CE2
ADV
WE
BWŸ
X
OE
ZZ
DQx/DQPx
}
CONTROL
REGISTER
CONTROL
LOGIC
K
OUTPUT
REGISTER
BUFFER
(X=a,b,c,d or a,b)
36 or 18
2
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. J
08/25/2014
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A
165-Ball, 13 mm x 15mm BGA
Bottom View
119-Ball, 14 mm x 22 mm BGA
Bottom View
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. J
08/25/2014
3
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A
PIN CONFIGURATION — 256K
x
36, 165-Ball PBGA (TOP VIEW)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
1
NC
NC
DQPc
DQc
DQc
DQc
DQc
NC
DQd
DQd
DQd
DQd
DQPd
NC
MODE
2
A
A
NC
DQc
DQc
DQc
DQc
NC
DQd
DQd
DQd
DQd
NC
NC
NC
3
CE
CE2
V
ddq
V
ddq
V
ddq
V
ddq
V
ddq
NC
V
ddq
V
ddq
V
ddq
V
ddq
V
ddq
A
A
4
BWc
BWd
V
SS
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
SS
A
A
5
BWb
BWa
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TdI
TMS
6
CE2
CLK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A1*
A0*
7
CKE
WE
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCK
8
ADV
OE
V
SS
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
SS
A
A
9
A
NC
V
ddq
V
ddq
V
ddq
V
ddq
V
ddq
NC
V
ddq
V
ddq
V
ddq
V
ddq
V
ddq
A
A
10
A
A
NC
DQb
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQa
NC
A
A
11
NC
NC
DQPb
DQb
DQb
DQb
DQb
ZZ
DQa
DQa
DQa
DQa
DQPa
NC
A
Note:
A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Pin Name
Address Inputs
Synchronous Burst Address Inputs
Synchronous Burst Address Advance/
Load
WE
Synchronous Read/Write Control
Input
CLK
Synchronous Clock
CKE
Clock Enable
CE, CE2,
CE2 Synchronous Chip Enable
BWx (x=a-d)
Synchronous Byte Write Inputs
OE
Output Enable
ZZ
Power Sleep Mode
Symbol
A
A0, A1
ADV
MODE
TCK, TDI
TDO, TMS
V
DD
NC
DQx
DQPx
V
DDQ
V
SS
Burst Sequence Selection
JTAG Pins
3.3V/2.5V Power Supply
No Connect
Data Inputs/Outputs
Parity Data I/O
Isolated output Power Supply
3.3V/2.5V
Ground
4
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. J
08/25/2014
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A
119-PIN
PBGA PACKAGE
CONFIGURATION
1
2
3
256K x 36 (TOP VIEW)
4
5
6
7
A
B
C
D
E
F
V
DDQ
NC
NC
DQc
DQc
V
DDQ
DQc
DQc
V
DDQ
DQd
DQd
V
DDQ
DQd
DQd
NC
NC
V
DDQ
A
CE2
A
DQPc
DQc
DQc
DQc
DQc
V
DD
DQd
DQd
DQd
DQd
DQPd
A
NC
TMS
A
A
A
V
SS
V
SS
V
SS
BWc
V
SS
NC
V
SS
BWd
V
SS
V
SS
V
SS
MODE
A
TDI
NC
ADV
V
DD
NC
CE
OE
A
WE
V
DD
CLK
NC
CKE
A
1
*
A
0
*
V
DD
A
TCK
A
A
A
Vss
Vss
Vss
BWb
Vss
NC
Vss
BWa
Vss
Vss
Vss
NC
A
TDO
A
CE2
A
DQPb
DQb
DQb
DQb
DQb
V
DD
DQa
DQa
DQa
DQa
DQPa
A
NC
NC
V
DDQ
NC
NC
DQb
DQb
V
DDQ
DQb
DQb
V
DDQ
DQa
DQa
V
DDQ
DQa
DQa
NC
ZZ
V
DDQ
G
H
J
K
L
M
N
P
R
T
U
Note:
A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Pin Name
Address Inputs
Synchronous Burst Address Inputs
Synchronous Burst Address Advance/
Load
WE
Synchronous Read/Write Control Input
CLK
Synchronous Clock
CKE
Clock Enable
CE
Synchronous Chip Select
CE2
Synchronous Chip Select
CE2
Synchronous Chip Select
BWx (x=a-d)
Synchronous Byte Write Inputs
Symbol
A
A0, A1
ADV
OE
ZZ
MODE
TCK, TDO
TMS, TDI
V
dd
V
SS
NC
DQa-DQd
DQPa-Pd
V
ddq
Output Enable
Power Sleep Mode
Burst Sequence Selection
JTAG Pins
Power Supply
Ground
No Connect
Data Inputs/Outputs
Parity Data I/O
Output Power Supply
Integrated Silicon Solution, Inc. — www.issi.com —
微控制器 MCU
