without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.- www.issi.com
Rev. 00A
7/05/2012
1
IS61QDPB21M18A/A1/A2
IS61QDPB251236A/A1/A2
Package ballout and description
x36 FBGA Ball Configuration (Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ#
Q27
D27
D28
Q29
Q30
D30
Doff#
D31
Q32
Q33
D33
D34
Q35
TDO
2
NC/SA
Q18
Q28
D20
D29
Q21
D22
V
REF
Q31
D32
Q24
Q34
D26
D35
TCK
1
3
NC/SA
D18
D19
Q19
Q20
D21
Q22
V
DDQ
D23
Q23
D24
D25
Q25
Q26
SA
1
4
W#
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
5
BW
2
#
BW
3
#
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
6
K#
K
SA
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
QVLD
ODT
7
BW
1
#
BW
0
#
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
8
R#
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
9
NC/SA
D17
D16
Q16
Q15
D14
Q13
V
DDQ
D12
Q12
D11
D10
Q10
Q9
SA
1
10
NC/SA
Q17
Q7
D15
D6
Q14
D13
V
REF
Q4
D3
Q11
Q1
D9
D0
TMS
1
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
Notes:
1.
The following balls are reserved for higher densities: 9A for 36M, 3A for 72M, 10A for 144Mb, and 2A for 288Mb.
x18 FBGA Ball Configuration (Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ#
NC
NC
NC
NC
NC
NC
Doff#
NC
NC
NC
NC
NC
NC
TDO
2
NC/SA
1
Q9
NC
D11
NC
Q12
D13
V
REF
NC
NC
Q15
NC
D17
NC
TCK
3
NC/SA
1
D9
D10
Q10
Q11
D12
Q13
V
DDQ
D14
Q14
D15
D16
Q16
Q17
SA
4
W#
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
5
BW
1
#
NC
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
6
K#
K
SA
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
QVLD
ODT
7
NC/SA
1
BW
0
#
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
8
R#
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
9
SA
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
SA
10
NC/SA
1
NC
Q7
NC
D6
NC
NC
V
REF
Q4
D3
NC
Q1
NC
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
Notes:
1.
The following balls are reserved for higher densities: 3A for 36M, 10A for 72M, 2A for 144Mb, and 7A for 288Mb.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. 00A
7/05/2012
2
IS61QDPB21M18A/A1/A2
IS61QDPB251236A/A1/A2
Ball Description
Symbol
K, K#
Type
Input
Description
Input clock: This input clock pair registers address and control inputs on the rising edge of K, and
registers data on the rising edge of K and the rising edge of K#. K# is ideally 180 degrees out of
phase with K. All synchronous inputs must meet setup and hold times around the clock rising
edges. These balls cannot remain VREF level.
Synchronous echo clock outputs: The edges of these outputs are tightly matched to the
synchronous data outputs and can be used as a data valid indication. These signals are free
running clocks and do not stop when Q tri-states.
DLL disable and reset input : when low, this input causes the DLL to be bypassed and reset the
previous DLL information. When high, DLL will start operating and lock the frequency after tCK lock
time. The device behaves in one clock read latency mode when the DLL is turned off. In this mode,
the device can be operated at a frequency of up to 167 MHz.
Valid output indicator: The Q Valid indicates valid output data. QVLD is edge aligned with CQ and
CQ#.
Synchronous address inputs: These inputs are registered and must meet the setup and hold times
around the rising edge of K. These inputs are ignored when device is deselected.
Synchronous data inputs: Input data must meet setup and hold times around the rising edges of K
and K# during WRITE operations. See BALL CONFIGURATION figures for ball site location of
individual signals.
The x18 device uses D0~D17. D18~D35 should be treated as NC pin.
The x36 device uses D0~D35.
Synchronous data outputs: Output data is synchronized to the respective CQ and CQ#, or to the
respective K and K# if C and /C are tied to high. This bus operates in response to R# commands.
See BALL CONFIGURATION figures for ball site location of individual signals.
The x18 device uses Q0~Q17. Q18~Q35 should be treated as NC pin.
The x36 device uses Q0~Q35.
Synchronous write: When low, this input causes the address inputs to be registered and a WRITE
cycle to be initiated. This input must meet setup and hold times around the rising edge of K.
Synchronous read: When low, this input causes the address inputs to be registered and a READ
cycle to be initiated. This input must meet setup and hold times around the rising edge of K.
Synchronous byte writes: When low, these inputs cause their respective byte to be registered and
written during WRITE cycles. These signals are sampled on the same edge as the corresponding
data and must meet setup and hold times around the rising edges of K and #K for each of the two
rising edges comprising the WRITE cycle. See Write Truth Table for signal to data relationship.
HSTL input reference voltage: Nominally VDDQ/2, but may be adjusted to improve system noise
margin. Provides a reference voltage for the HSTL input buffers.
Power supply: 1.8 V nominal. See DC Characteristics and Operating Conditions for range.
Power supply: Isolated output buffer supply. Nominally 1.5 V. See DC Characteristics and
Operating Conditions for range.
Ground of the device
Output impedance matching input: This input is used to tune the device outputs to the system data
bus impedance. Q and CQ output impedance are set to 0.2xRQ, where RQ is a resistor from this
ball to ground. This ball can be connected directly to VDDQ, which enables the minimum
impedance mode. This ball cannot be connected directly to VSS or left unconnected.
In ODT (On Die Termination) enable devices, the ODT termination values tracks the value of RQ.
The ODT range is selected by ODT control input.
IEEE1149.1 input pins for JTAG.
IEEE1149.1 output pins for JTAG.
No connect: These signals should be left floating or connected to ground to improve package heat
dissipation.
ODT control; Refer to SRAM features for the details.
CQ, CQ#
Output
Doff#
QVLD
SA
Input
Output
Input
D0 - Dn
Input
Q0 - Qn
Output
W#
R#
BW
x
#
V
REF
V
DD
V
DDQ
V
SS
Input
Input
Input
Input
reference
Power
Power
Ground
ZQ
Input
TMS, TDI, TCK
TDO
NC
ODT
Input
Output
N/A
Input
Integrated Silicon Solution, Inc.- www.issi.com
Rev. 00A
7/05/2012
3
IS61QDPB21M18A/A1/A2
IS61QDPB251236A/A1/A2
SRAM Features description
Block Diagram
36 (18)
D (Data-In)
Data
Register
72 (36)
72 (36)
72 (36)
36 (18)
36 (18)
Output Driver
Q (Data-out)
QVLD
2
CQ, CQ#
(Echo Clocks)
Write
Driver
Address Decoder
Sense Amplifiers
20 (21)
Address
Register
72 (36)
72 (36)
19 (20)
2M x 36
(4M x 18)
Memory Array
Output
Register
72(36)
Output Select
Address
QVLD
2
R#
W#
BW
x
#
4 (2)
Control
Logic
CQ, CQ#
(Echo Clocks)
K
K#
Clock
Generator
Select Output Control
Doff#
Note: Numerical values in parentheses refer to the x18 device configuration
.
Read Operations
The SRAM operates continuously in a burst-of-two mode. Read cycles are started by registering R# in active low state
at the rising edge of the K clock. R# can be activated every other cycle because two full cycles are required to
complete the burst of two in DDR mode. A set of free-running echo clocks, CQ and CQ#, are produced internally with
timings identical to the data-outs. The echo clocks can be used as data capture clocks by the receiver device.
The data corresponding to the first address is clocked two and half cycles later by the rising edge of the K# clock. The
data corresponding to the second burst is clocked three cycles later by the following rising edge of the K clock.
A NOP operation (R# is high) does not terminate the previous read.
Write Operations
Write operations can also be initiated at every rising edge of the K clock with first data whenever W# is low. The write
address is provided half cycle with second data later, registered by the rising edge of K#, so the write always occurs in
bursts of two.
The write data is provided in an ‘early write’ mode; that is, the data-in corresponding to the first address of the burst, is
presented half cycle before the rising edge of the following K clock. The data-in corresponding to the second write
burst address follows next, registered by the rising edge of K#.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. 00A
7/05/2012
4
IS61QDPB21M18A/A1/A2
IS61QDPB251236A/A1/A2
The data-in provided for writing is initially kept in write buffers. The information in these buffers is written into the array
on the third write cycle. A read cycle to the last write address produces data from the write buffers. Similarly, a read
address followed by the same write address produces the latest write data. The SRAM maintains data coherency.
During a write, the byte writes independently control which byte of any of the four burst addresses is written (see
X18/X36 Write Truth Tables
and
Timing Reference Diagram for Truth Table).
Whenever a write is disabled (W# is high at the rising edge of K), data is not written into the memory.
RQ Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin on the SRAM and V
SS
to enable the SRAM to adjust
its output driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the
SRAM. For example, an RQ of 250Ω results in a driver impedance of 50Ω. The allowable range of RQ to guarantee
impedance matching is between 175Ω and 350Ω at V
DDQ
=1.5V. The RQ resistor should be placed less than two inches
away from the ZQ ball on the SRAM module. The capacitance of the loaded ZQ trace must be less than 7.5pF.
The ZQ pin can also be directly connected to V
DDQ
to obtain a minimum impedance setting. ZQ must never be
connected to V
SS
.
Programmable Impedance and Power-Up Requirements
Periodic readjustment of the output driver impedance is necessary as the impedance is greatly affected by drifts in
supply voltage and temperature. During power-up, the driver impedance is in the middle of allowable impedances
value. The final impedance value is achieved within 1024 clock cycles.
Depth Expansion
Separate input and output ports enable easy depth expansion, as each port can be selected and deselected
independently. Read and write operations can occur simultaneously without affecting each other. Also, all pending
read and write transactions are always completed prior to deselecting the corresponding port.
Valid Data Indicator (QVLD)
A data valid pin (QVLD) is available to assist in high-speed data output capture. This output signal is edge-aligned with
the echo clock and is asserted HIGH half a cycle before valid read data is available and asserted LOW half a cycle
before the final valid read data arrives.
Delay Locked Loop (DLL)
Delay Locked Loop (DLL) is a new system to align the output data coincident with clock rising or falling edge to
enhance the output valid timing characteristics. It is locked to the clock frequency and is constantly adjusted to match
the clock frequency. Therefore device can have stable output over the temperature and voltage variation.
DLL has a limitation of locking range and jitter adjustment which are specified as tKHKH and tKCvar respectively in the
AC timing characteristics. In order to turn this feature off, applying logic low to the Doff# pin will bypass this. In the DLL
off mode, the device behaves with one clock cycle latency and a longer access time which is known in DDR-I or legacy
QUAD mode.
The DLL can also be reset without power down by toggling Doff# pin low to high or stopping the input clocks K and K#
for a minimum of 30ns.(K and K# must be stayed either at higher than VIH or lower than VIL level. Remaining Vref is
not permitted.) DLL reset must be issued when power up or when clock frequency changes abruptly. After DLL being
reset, it gets locked after 2048 cycles of stable clock.
