IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
512K x36 and 1024K x18 18Mb,
SYNCHRONOUS FLOW-THROUGH SRAM
OCTOBER 2015
FEATURES
•
•
•
•
•
•
•
•
•
•
•
Internal self-timed write cycle
Individual Byte Write Control and Global Write
Clock controlled, registered address, data and
control
Burst sequence control using MODE input
Three chip enable option for simple depth
expansion and address pipelining
Common data inputs and data outputs
Auto Power-down during deselect
Single cycle deselect
Snooze MODE for reduced-power standby
JEDEC 100-pin QFP, 165-ball BGA and 119-ball
BGA packages
Power supply:
LF: V
DD
3.3V (± 5%), V
DDQ
3.3V/2.5V (± 5%)
VF: V
DD
2.5V (± 5%), V
DDQ
2.5V (± 5%)
VVF: V
DD
1.8V (± 5%), V
DDQ
1.8V (± 5%)
JTAG Boundary Scan for BGA packages
Commercial, Industrial and Automotive
temperature support
Lead-free available
For leaded options, please contact ISSI
DESCRIPTION
The 18Mb product family features high-speed, low-
power synchronous static RAMs designed to provide
burstable, high-performance memory for
communication and networking applications. The
IS61(64)LF/VF/VVF51236(32)B organized as 524,288
words by 36(32)bits. The IS61(64)LF/VF/VVF102418B
are organized as 1,048,576 words by 18 bits.
Fabricated with ISSI's advanced CMOS technology,
the device integrates a 2-bit burst counter, high-speed
SRAM core, and high-drive capability outputs into a
single monolithic circuit. All synchronous inputs pass
through registers controlled by a positive-edge-
triggered single clock input.
Write cycles are internally self-timed and are initiated
by the rising edge of the clock input. Write cycles can
be one to four bytes wide as controlled by the write
control inputs.
Separate byte enables allow individual bytes to be
written. The byte write operation is performed by using
the byte write enable (/BWE) input combined with one
or more individual byte write signals (/BWx). In
addition, Global Write (/GW) is available for writing all
bytes at one time, regardless of the byte write controls.
Bursts can be initiated with either /ADSP (Address
Status Processor) or /ADSC (Address Status Cache
Controller) input pins. Subsequent burst addresses can
be generated internally and controlled by the /ADV
(burst address advance) input pin.
The mode pin is used to select the burst sequence
order. Linear burst is achieved when this pin is tied
LOW. Interleave burst is achieved when this pin is tied
HIGH or left floating
•
•
•
•
FAST ACCESS TIME
Symbol
t
KQ
t
KC
Parameter
Clock Access
Time
Cycle time
Frequency
-6.5
6.5
7.5
133
-7.5
7.5
8.5
117
Units
ns
ns
MHz
Copyright © 2015 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C
09/12/2015
1
IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
BLOCK DIAGRAM
E
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C
09/12/2015
2
IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
PIN CONFIGURATION
512K x 36, 165-Ball BGA (Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
2
3
4
5
6
7
8
9
10
11
NC
NC
DQPc
DQc
DQc
DQc
DQc
NC
DQd
DQd
DQd
DQd
DQPd
NC
MODE
A
A
NC
DQc
DQc
DQc
DQc
V
SS
DQd
DQd
DQd
DQd
NC
NC
NC
/CE
CE2
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
/BWc
/BWd
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
/BWb
/BWa
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
/CE2
CLK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
A1*
A0*
/BWE
/GW
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCK
/ADSC
/OE
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
/ADV
/ADSP
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
A
A
NC
DQb
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQa
NC
A
A
NC
NC
DQPb
DQb
DQb
DQb
DQb
ZZ
DQa
DQa
DQa
DQa
DQPa
A
A
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
CLK
A0,A1
A
/ADV
/ADSP
/ADSC
MODE
/CE,CE2,/CE2
/BWE
/BWx (x=a-d)
/GW
/OE
DQx
DQPx
TCK,TDI,
TDO,TMS
ZZ
NC
V
DD
V
DDQ
V
SS
Pin Name
Synchronous Clock
Synchronous Burst Address Inputs
Address Inputs
Synchronous Burst Address Advance
Address Status Processor
Address Status Controller
Burst Sequence Selection
Synchronous Chip Enable
Byte Write Enable
Synchronous Byte Write Inputs
Global Write Enable
Output Enable
Data Inputs/Outputs
Parity Data I/O
JTAG Pins
Power Sleep Mode
No Connect
Power Supply
I/O Power Supply
Ground
3
Bottom View
165-Ball, 13 mm x 15mm BGA
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C
09/12/2015
IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
512K x 32, 165-Ball BGA (Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
2
3
4
5
6
7
8
9
10
11
NC
NC
NC
DQc
DQc
DQc
DQc
NC
DQd
DQd
DQd
DQd
NC
NC
MODE
A
A
NC
DQc
DQc
DQc
DQc
V
SS
DQd
DQd
DQd
DQd
NC
NC
NC
/CE
CE2
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
/BWc
/BWd
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
/BWb
/BWa
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
/CE2
CLK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
A1*
A0*
/BWE
/GW
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCK
/ADSC
/OE
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
/ADV
/ADSP
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
A
A
NC
DQb
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQa
NC
A
A
NC
NC
NC
DQb
DQb
DQb
DQb
ZZ
DQa
DQa
DQa
DQa
NC
A
A
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
CLK
A0,A1
A
/ADV
/ADSP
/ADSC
MODE
/CE,CE2,/CE2
/BWE
/BWx (x=a-d)
/GW
/OE
DQx
DQPx
TCK,TDI,
TDO,TMS
ZZ
NC
V
DD
V
DDQ
V
SS
Pin Name
Synchronous Clock
Synchronous Burst Address Inputs
Address Inputs
Synchronous Burst Address Advance
Address Status Processor
Address Status Controller
Burst Sequence Selection
Synchronous Chip Enable
Byte Write Enable
Synchronous Byte Write Inputs
Global Write Enable
Output Enable
Data Inputs/Outputs
Parity Data I/O
JTAG Pins
Power Sleep Mode
No Connect
Power Supply
I/O Power Supply
Ground
Bottom View
165-Ball, 13 mm x 15mm BGA
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C
09/12/2015
4
IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B
IS61LF102418B/IS61VF102436B/IS61VVF102418B
1024K x 18, 165-Ball BGA (Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
2
3
4
5
6
7
8
9
10
11
NC
NC
NC
NC
NC
NC
NC
NC
DQb
DQb
DQb
DQb
DQPb
NC
MODE
A
A
NC
DQb
DQb
DQb
DQb
V
SS
NC
NC
NC
NC
NC
NC
NC
/CE
CE2
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
/BWb
NC
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
NC
/BWa
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
/CE2
CLK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
A1*
A0*
/BWE
/GW
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCK
/ADSC
/OE
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
/ADV
/ADSP
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
A
A
NC
NC
NC
NC
NC
NC
DQa
DQa
DQa
DQa
NC
A
A
A
NC
DQPa
DQa
DQa
DQa
DQa
ZZ
NC
NC
NC
NC
NC
A
A
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
CLK
A0,A1
A
/ADV
/ADSP
/ADSC
MODE
/CE,CE2,/CE2
/BWE
/BWx (x=a-b)
/GW
/OE
DQx
DQPx
TCK,TDI,
TDO,TMS
ZZ
NC
V
DD
V
DDQ
V
SS
Pin Name
Synchronous Clock
Synchronous Burst Address Inputs
Address Inputs
Synchronous Burst Address
Advance
Address Status Processor
Address Status Controller
Burst Sequence Selection
Synchronous Chip Enable
Byte Write Enable
Synchronous Byte Write Inputs
Global Write Enable
Output Enable
Data Inputs/Outputs
Parity Data I/O
JTAG Pins
Power Sleep Mode
No Connect
Power Supply
I/O Power Supply
Ground
Bottom View
165-Ball, 13 mm x 15mm BGA
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C
09/12/2015
5
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