IS62LV12816L
IS62LV12816L
128K x 16 CMOS STATIC RAM
ISSI
DESCRIPTION
ISSI
®
®
ADVANCE INFORMATION
AUGUST 1998
1
FEATURES
• High-speed access time: 70, 100, and 120 ns
• CMOS low power operation
– 120 mW (typical) operating
– 6
µW
(typical) CMOS standby
• TTL compatible interface levels
• Single 3V
±
10% V
CC
power supply
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• Industrial temperature available
• Available in the 44-pin TSOP (Type II) and
48-pin mini BGA
The
ISSI
IS62LV12816L is a high-speed, 2,097,152-bit static
RAM organized as 131,072 words by 16 bits. It is fabricated
using
ISSI
's high-performance CMOS technology. This highly
reliable process coupled with innovative circuit design
techniques, yields high-performance and low power
consumption devices.
When
CE
is HIGH (deselected), the device assumes a standby
mode at which the power dissipation can be reduced down
with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs,
CE
and
OE
. The active LOW Write
Enable (
WE
) controls both writing and reading of the memory.
A data byte allows Upper Byte (
UB
) and Lower Byte (
LB
)
access.
The IS62LV12816L is packaged in the JEDEC standard
44-pin TSOP (Type II) and 48-pin mini BGA.
2
3
4
5
6
FUNCTIONAL BLOCK DIAGRAM
7
A0-A16
DECODER
128K x 16
MEMORY ARRAY
8
9
VCC
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
I/O
DATA
CIRCUIT
COLUMN I/O
10
11
CE
OE
WE
UB
LB
The specification contains ADVANCE INFORMATION. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible
product. We assume no responsibility for any errors which may appear in this publication. © Copyright 1998, Integrated Silicon Solution, Inc.
CONTROL
CIRCUIT
12
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION
SR002-0C
08/20/98
1
IS62LV12816L
PIN CONFIGURATIONS
44-Pin TSOP (Type II)
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
Vcc
GND
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
ISSI
48-Pin mini BGA
1
A
B
C
D
E
F
G
H
LB
I/O
8
I/O
9
GND
Vcc
I/O
14
I/O
15
NC
®
2
OE
UB
I/O
10
I/O
11
I/O
12
I/O
13
NC
A8
3
A0
A3
A5
NC
NC
A14
A12
A9
4
A1
A4
A6
A7
A16
A15
A13
A10
5
A2
CE
I/O
1
I/O
3
I/O
4
I/O
5
WE
A11
6
N/C
I/O
0
I/O
2
Vcc
GND
I/O
6
I/O
7
NC
PIN DESCRIPTIONS
A0-A16
I/O0-I/O15
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Output Enable Input
Write Enable Input
LB
UB
NC
Vcc
GND
Lower-byte Control (I/O0-I/O7)
Upper-byte Control (I/O8-I/O15)
No Connection
Power
Ground
CE
OE
WE
TRUTH TABLE
Mode
Not Selected
Output Disabled
Read
WE
X
H
X
H
H
H
L
L
L
CE
H
L
L
L
L
L
L
L
L
OE
X
H
X
L
L
L
X
X
X
LB
X
X
H
L
H
L
L
H
L
UB
X
X
H
H
L
L
H
L
L
I/O PIN
I/O0-I/O7
I/O8-I/O15
High-Z
High-Z
High-Z
D
OUT
High-Z
D
OUT
D
IN
High-Z
D
IN
High-Z
High-Z
High-Z
High-Z
D
OUT
D
OUT
High-Z
D
IN
D
IN
Vcc Current
I
SB
1
, I
SB
2
I
CC
I
CC
Write
I
CC
2
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION
SR002-0C
08/20/98
IS62LV12816L
OPERATING RANGE
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
V
CC
3.0V
±
10%
3.0V
±
10%
ISSI
®
1
Unit
V
°C
V
°C
W
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
T
BIAS
V
CC
T
STG
P
T
Parameter
Terminal Voltage with Respect to GND
Temperature Under Bias
Vcc Related to GND
Storage Temperature
Power Dissipation
Value
–0.5 to Vcc+0.5
–40 to +85
–0.3 to +4.0
–65 to +150
1.0
2
3
4
5
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
Symbol
V
OH
V
OL
V
IH
V
IL(1)
I
LI
I
LO
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage
Output Leakage
GND
≤
V
IN
≤
V
CC
GND
≤
V
OUT
≤
V
CC
, Outputs Disabled
Test Conditions
V
CC
= Min., I
OH
= –1 mA
V
CC
= Min., I
OL
= 2.1 mA
Min.
2.0
—
2.2
–0.2
–1
–1
Max.
—
0.4
V
CC
+ 0.2
0.4
1
1
Unit
V
V
V
V
µA
µA
6
7
8
9
Notes:
1. V
IL
(min.) = –2.0V for pulse width less than 10 ns.
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
Symbol Parameter
I
CC
I
SB
1
Vcc Dynamic Operating
Supply Current
TTL Standby Current
(TTL Inputs)
CMOS Standby
Current (CMOS Inputs)
Test Conditions
V
CC
= Max.,
I
OUT
= 0 mA, f = f
MAX
V
CC
= Max.,
V
IN
= V
IH
or V
IL
CE
≥
V
IH
, f = 0
V
CC
= Max.,
CE
≥
V
CC
– 0.2V,
V
IN
≥
V
CC
– 0.2V, or
V
IN
≤
0.2V, f = 0
Com.
Ind.
Com.
Ind.
Com.
Ind.
-70
Min. Max.
—
—
—
—
—
—
40
60
0.4
1.0
15
25
-100
Min. Max.
—
—
—
—
—
—
30
50
0.4
1.0
15
25
-120
Min. Max.
—
—
—
—
—
—
20
40
0.4
1.0
15
25
Unit
mA
mA
10
11
I
SB
2
µA
12
Note:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION
SR002-0C
08/20/98
3
IS62LV12816L
CAPACITANCE
(1)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Input/Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
6
8
Unit
pF
pF
ISSI
®
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0.4V to 2.2V
5 ns
1.5V
See Figures 1 and 2
AC TEST LOADS
3070
Ω
2.8V
2.8V
3070
Ω
OUTPUT
100 pF
Including
jig and
scope
Figure 1
OUTPUT
3150
Ω
5 pF
Including
jig and
scope
Figure 2
3150
Ω
4
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION
SR002-0C
08/20/98
IS62LV12816L
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
Symbol
Parameter
Read Cycle Time
Address Access Time
Output Hold Time
-70
Min. Max.
70
—
10
—
—
—
5
0
10
—
0
0
—
70
—
70
35
25
—
25
—
35
25
—
-100
Min. Max.
100
—
15
—
—
—
5
0
10
—
0
0
—
100
—
100
50
30
—
30
—
50
35
—
-120
Min. Max.
120
—
15
—
—
0
5
0
10
—
0
0
—
120
—
120
60
40
—
40
—
60
50
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ISSI
®
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
HZOE
(2)
t
LZOE
(2)
t
HZCE
(2)
t
LZCE
(2)
t
BA
t
HZB
t
LZB
1
2
3
4
5
6
7
8
CE
Access Time
OE
Access Time
OE
to High-Z Output
OE
to Low-Z Output
CE
to High-Z Output
CE
to Low-Z Output
LB
,
UB
Access Time
LB
,
UB
to High-Z Output
LB
,
UB
to Low-Z Output
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels
of 0.4 to 2.2V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured
±500
mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS
READ CYCLE NO. 1
(1,2)
(Address Controlled) (
CE
=
OE
= V
IL
,
UB
or
LB
= V
IL
)
t
RC
ADDRESS
t
AA
t
OHA
t
OHA
DATA VALID
9
D
OUT
PREVIOUS DATA VALID
10
11
12
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION
SR002-0C
08/20/98
5
RF/无线
