IS62LV2568L
IS62LV2568LL
IS62LV2568L
IS62LV2568LL
256K x 8 LOW POWER and LOW V
++
CMOS STATIC RAM
FEATURES
Access times of 55, 70, 100 ns
Low active power: 126 mW (max, L, LL)
Low standby power: 36 µW (max, L) and 7.2
µW (max, LL) CMOS standby
Low data retention voltage: 1.5V (min.)
Available in Low Power (-L) and Ultra-Low
Power (-LL)
Output Enable (OE) and two Chip Enable
TTL compatible inputs and outputs
Single 2.7V-3.6V power supply
Available in the 32-pin 8x20mm TSOP-1, 32-pin
8x13.4mm TSOP-1 and 48-pin 6*8mm TF-BGA
DESCRIPTION
The
1+51
IS62LV2568L and IS62LV2568LL are low power
and low V
CC
, 262,144-bit words by 8 bits CMOS static RAMs.
They are fabricated using
1+51
's high-performance CMOS
technology. This highly reliable process coupled with innova-
tive circuit design techniques, yields higher performance and
low power consumption devices.
When
CE1
is HIGH or CE2 is LOW (deselected), the device
assumes a standby mode at which the power dissipation can
be reduced by using CMOS input levels.
Easy memory expansion is provided by using two Chip Enable
inputs,
CE1
and CE2. The active LOW Write Enable (WE)
controls both writing and reading of the memory.
The IS62LV2568L and IS62LV2568LL are available in 32-pin
8*20mm TSOP-1, 8*13.4mm TSOP-1 and 48-pin 6*8mm TF-
BGA.
FUNCTIONAL BLOCK DIAGRAM
A0-A17
DECODER
2048 x 128 x 8
MEMORY ARRAY
VCC
GND
I/O
DATA
CIRCUIT
I/O0-I/O7
COLUMN I/O
CE1
CE2
OE
WE
CONTROL
CIRCUIT
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
SR025_0C
1
IS62LV2568L
IS62LV2568LL
PIN CONFIGURATIONS
32-Pin 8*20mm TSOP-1, 8*13.4mm STSOP-1
A11
A9
A8
A13
WE
CE2
A15
Vcc
A17
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
48-Pin 6*8mm TF-BGA
1
A
B
C
D
E
F
G
H
A0
I/O
4
I/O
5
GND
Vcc
I/O
6
I/O
7
A9
2
A1
A2
3
CE2
WE
NC
4
A3
A4
A5
5
A6
A7
6
A8
I/O
0
I/O
1
Vcc
GND
NC
OE
A10
CE1
A11
A17
A16
A12
A15
A13
I/O
2
I/O
3
A14
PIN DESCRIPTIONS
A0-A17
CE1
CE2
OE
WE
I/O0-I/O7
NC
Vcc
GND
Address Inputs
Chip Enable 1 Input
Chip Enable 2 Input
Output Enable Input
Write Enable Input
Data Input/Output
No Connection
Power
Ground
OPERATING RANGE
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
40°C to +85°C
V
CC
2.7V - 3.6V
2.7V - 3.6V
2
Integrated Circuit Solution Inc.
SR025_0C
IS62LV2568L
IS62LV2568LL
TRUTH TABLE
Mode
Not Selected
(Power-down)
Output Disabled
Read
Write
WE
X
X
H
H
L
CE1
H
X
L
L
L
CE2
X
L
H
H
H
OE
X
X
H
L
X
I/O Operation
High-Z
High-Z
High-Z
D
OUT
D
IN
Vcc Current
I
SB
, I
SB
I
SB
, I
SB
I
CC
I
CC
I
CC
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
V
CC
T
BIAS
T
STG
P
T
Parameter
Terminal Voltage with Respect to GND
Vcc related to GND
Temperature Under Bias
Storage Temperature
Power Dissipation
Value
0.5 to Vcc + 0.5
0.3 to +4.0
40 to +85
65 to +150
0.7
Unit
V
V
°C
°C
W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
CAPACITANCE
(1)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
6
8
Unit
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
Symbol
V
OH
V
OL
V
IH
V
IL
(1)
I
LI
I
LO
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
(1)
Input Leakage
Output Leakage
Test Conditions
V
CC
= Min., I
OH
= 1.0 mA
V
CC
= Min., I
OL
= 2.1 mA
Min.
2.2
2.2
0.3
1
1
Max.
0.4
V
CC
+ 0.3
0.4
1
1
Unit
V
V
V
V
µA
µA
GND
≤
V
IN
≤
V
CC
GND
≤
V
OUT
≤
V
CC
Notes:
1. V
IL
= 2.0V for pulse width less than 10 ns.
Integrated Circuit Solution Inc.
SR025_0C
3
IS62LV2568L
IS62LV2568LL
IS62LV2568L POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
Symbol Parameter
I
CC
I
SB
Vcc Dynamic Operating
Supply Current
TTL Standby Current
(TTL Inputs)
CMOS Standby
Current (CMOS Inputs)
Test Conditions
V
CC
= Max.,
I
OUT
= 0 mA, f = f
MAX
Com.
Ind.
-55
Min. Max.
40
45
0.4
1.0
35
50
-70
Min. Max.
30
35
0.4
1.0
35
50
-100
Min. Max.
20
25
0.4
1.0
35
50
Unit
mA
mA
V
CC
= Max.,
Com.
V
IN
= V
IH
or V
IL
,
Ind.
CE1
≥
V
IH
or CE2
≤
V
IL
, f = 0
V
CC
= Max., f = 0
Com.
CE1
≥
V
CC
0.2V,
Ind.
CE2
≤
0.2V,
or V
IN
≥
V
CC
0.2V, V
IN
≤
0.2V
I
SB
µA
Note:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
IS62LV2568LL POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
Symbol Parameter
I
CC
I
SB
Vcc Dynamic Operating
Supply Current
TTL Standby Current
(TTL Inputs)
CMOS Standby
Current (CMOS Inputs)
Test Conditions
V
CC
= Max.,
I
OUT
= 0 mA, f = f
MAX
Com.
Ind.
-55
Min. Max.
40
45
0.4
1.0
10
15
-70
Min. Max.
30
35
0.4
1.0
10
15
-100
Min. Max.
20
25
0.4
1.0
10
15
Unit
mA
mA
V
CC
= Max.,
Com.
V
IN
= V
IH
or V
IL
,
Ind.
CE1
≥
V
IH
or CE2
≤
V
IL
, f = 0
V
CC
= Max., f = 0
Com.
CE
≥
V
CC
0.2V,
Ind.
CE2
≤
0.2V,
or V
IN
≥
V
CC
0.2V, V
IN
≤
0.2V
I
SB
µA
Note:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
4
Integrated Circuit Solution Inc.
SR025_0C
IS62LV2568L
IS62LV2568LL
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
Symbol
Parameter
Read Cycle Time
Address Access Time
Output Hold Time
CE1
Access Time
CE2 Access Time
OE
Access Time
-55
Min. Max.
55
10
5
10
10
0
55
55
55
30
20
20
-70
Min. Max.
70
10
5
0
10
10
0
70
70
70
35
25
25
-100
Min. Max.
100
15
5
0
10
10
0
100
100
100
50
30
30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
RC
t
AA
t
OHA
t
ACE
1
t
ACE
2
t
DOE
t
LZOE
(2)
OE
to Low-Z Output
t
HZOE
(2)
OE
to High-Z Output
t
LZCE
1
(2)
CE1
to Low-Z Output
t
LZCE
2
(2)
CE2 to Low-Z Output
t
HZCE
(2)
CE1
or CE2 to Low-Z Output
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels
of 0.4V to 2.2V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0.4V to 2.2V
5 ns
1.5V
See Figures 1 and 2
AC TEST LOADS
1 TTL
OUTPUT
100 pF
Including
jig and
scope
OUTPUT
5 pF
Including
jig and
scope
1 TTL
Figure 1
Figure 2
Integrated Circuit Solution Inc.
SR025_0C
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