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IS62V6416BLL-12TI

Standard SRAM, 64KX16, 120ns, CMOS, PDSO44, PLASTIC, TSOP2-44

器件类别:存储    存储   

厂商名称:Integrated Silicon Solution ( ISSI )

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器件参数
参数名称
属性值
是否无铅
含铅
是否Rohs认证
不符合
厂商名称
Integrated Silicon Solution ( ISSI )
零件包装代码
TSOP2
包装说明
PLASTIC, TSOP2-44
针数
44
Reach Compliance Code
compliant
ECCN代码
EAR99
最长访问时间
120 ns
其他特性
TTL COMPATIBLE
JESD-30 代码
R-PDSO-G44
JESD-609代码
e0
长度
18.41 mm
内存密度
1048576 bit
内存集成电路类型
STANDARD SRAM
内存宽度
16
湿度敏感等级
3
功能数量
1
端子数量
44
字数
65536 words
字数代码
64000
工作模式
ASYNCHRONOUS
最高工作温度
85 °C
最低工作温度
-40 °C
组织
64KX16
封装主体材料
PLASTIC/EPOXY
封装代码
TSOP2
封装形状
RECTANGULAR
封装形式
SMALL OUTLINE, THIN PROFILE
并行/串行
PARALLEL
峰值回流温度(摄氏度)
NOT SPECIFIED
认证状态
Not Qualified
座面最大高度
1.2 mm
最大供电电压 (Vsup)
3.3 V
最小供电电压 (Vsup)
2.7 V
标称供电电压 (Vsup)
3 V
表面贴装
YES
技术
CMOS
温度等级
INDUSTRIAL
端子面层
Tin/Lead (Sn/Pb)
端子形式
GULL WING
端子节距
0.8 mm
端子位置
DUAL
处于峰值回流温度下的最长时间
NOT SPECIFIED
宽度
10.16 mm
Base Number Matches
1
文档预览
IS62V6416BLL
64K x 16 LOW VOLTAGE,
ULTRA LOW POWER CMOS STATIC RAM
FEATURES
• Access time: 100 and 120 ns
• CMOS low power operation
• TTL compatible interface levels
• Single 2.7V-3.3V power supply
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• Industrial temperature available
• Available in Jedec Std 44-pin SOJ package,
44-pin TSOP (Type II), and 48-pin mini BGA
ISSI
DESCRIPTION
®
MARCH 2000
The
ISSI
IS62V6416BLL is an ultra-low power, 1,048,576-bit
static RAM organized as 65,536 words by 16 bits. It is
fabricated using
ISSI
's high-performance CMOS technology.
This highly reliable process coupled with innovative circuit
design techniques yields access times as fast as 100 ns with
low power consumption.
When
CS
is HIGH (deselected) or when
CS
is LOW and both
LB
and
UB
are HIGH, the device assumes a standby mode at
which the power dissipation can be reduced down with CMOS
input levels.
Easy memory expansion is provided by using Chip Select and
Output Enable inputs,
CS
and
OE.
The active LOW Write
Enable (WE) controls both writing and reading of the memory.
A data byte allows Upper Byte (UB) and Lower Byte (LB) access.
FUNCTIONAL BLOCK DIAGRAM
A0-A15
DECODER
64K x 16
MEMORY ARRAY
VCC
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
I/O
DATA
CIRCUIT
COLUMN I/O
CS
OE
WE
UB
LB
CONTROL
CIRCUIT
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/17/00
1
IS62V6416BLL
PIN CONFIGURATIONS
44-Pin SOJ
A4
A3
A2
A1
A0
CS
I/O0
I/O1
I/O2
I/O3
Vcc
GND
I/O4
I/O5
I/O6
I/O7
WE
A15
A14
A13
A12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
ISSI
44-Pin TSOP
®
A4
A3
A2
A1
A0
CS
I/O0
I/O1
I/O2
I/O3
Vcc
GND
I/O4
I/O5
I/O6
I/O7
WE
A15
A14
A13
A12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
48-Pin mini BGA
(Top View)
1
2
3
4
5
6
PIN DESCRIPTIONS
A0-A15
I/O0-I/O15
CS
OE
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Output Enable Input
Write Enable Input
Lower-byte Control (I/O0-I/O7)
Upper-byte Control (I/O8-I/O15)
No Connection
Power
Ground
A
B
C
D
E
F
G
H
LB
I/O
8
I/O
9
GND
Vcc
I/O
14
I/O
15
NC
OE
UB
I/O
10
I/O
11
I/O
12
I/O
13
NC
A8
A0
A3
A5
NC
NC
A14
A12
A9
A1
A4
A6
A7
NC
A15
A13
A10
A2
CS
I/O
1
I/O
3
I/O
4
I/O
5
WE
A11
N/C
I/O
0
I/O
2
Vcc
GND
I/O
6
I/O
7
NC
WE
LB
UB
NC
Vcc
GND
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/17/00
IS62V6416BLL
TRUTH TABLE
Mode
Not Selected
Output Disabled
Read
WE
X
X
H
H
H
H
L
L
L
CS
H
L
L
L
L
L
L
L
L
OE
X
X
H
L
L
L
X
X
X
LB
X
H
L
L
H
L
L
H
L
UB
X
H
L
H
L
L
H
L
L
I/O Pin
I/O0-I/O7
I/O8-I/O15
High-Z
High-Z
High-Z
D
OUT
High-Z
D
OUT
D
IN
High-Z
D
IN
High-Z
High-Z
High-Z
High-Z
D
OUT
D
OUT
High-Z
D
IN
D
IN
ISSI
Vcc Current
I
SB
1, I
SB
2
I
SB
1, I
SB
2
I
CC
I
CC
®
1
2
3
Write
I
CC
4
5
6
7
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing and Reference Level
Output Load
Unit
0 to 3V
(1)
5 ns
1.5V
(1)
See Figures 1 and 2
AC TEST LOADS
1076
3V
OUTPUT
30 pF
Including
jig and
scope
Figure 1.
1076
3V
OUTPUT
1262
5 pF
Including
jig and
scope
Figure 2.
8
9
1262
10
11
THEVENIN EQUIVALENT
581
OUTPUT
Figure 3.
12
1.61V
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/17/00
3
IS62V6416BLL
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Parameter
V
TERM
T
STG
P
T
I
OUT
Storage Temperature
Power Dissipation
DC Output Current (LOW)
Value
–65 to +150
1.5
20
Unit
V
°C
W
mA
ISSI
®
Terminal Voltage with Respect to GND –0.5 to Vcc +0.5
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING RANGE
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
V
CC
2.7V (Min.) to 3.3V (Max.)
2.7V (Min.) to 3.3V (Max.)
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range Unless Otherwise Specified)
Symbol
V
OH
V
OL
V
IH
V
IL(1)
I
LI
I
LO
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage
Output Leakage
GND
V
IN
V
CC
GND
V
OUT
V
CC
, Outputs Disabled
Test Conditions
V
CC
= Min., I
OH
= –1 mA
V
CC
= Min., I
OL
= 2.1 mA
Min.
2.2
2.0
–0.2
–1
–1
Max.
0.4
V
CC
+ 0.3
0.4
1
1
Unit
V
V
V
V
µA
µA
Note:
1. V
IL
(min.) = –1.5V for pulse width less than 30 ns.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/17/00
IS62V6416BLL
ISSI
-100
-120
Min.
Max.
30
40
0.3
0.3
Unit
mA
35
45
0.3
0.3
Test Conditions
V
CC
= Max.,
I
OUT
= 0 mA, f = f
MAX
CS
= V
IH
V
CC
= Max.,
V
IN
= V
IH
or V
IL
CS
V
IH
, f = 0
Com.
Ind.
Com.
Ind.
Min.
Max.
®
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range Unless Otherwise Specified)
Symbol
I
CC
Parameter
Vcc Dynamic
Operating
Supply Current
TTL Standby
Current
(TTL Inputs)
OR
ULB Control
1
2
3
I
SB
1
mA
V
CC
= Max., V
IN
= V
IH
or V
IL
CS
= V
IL
, f = 0,
UB
= V
IH
,
LB
= V
IH
V
CC
= Max.,
CS
V
CC
– 0.2V
V
IN
0.2V, f = 0
Com.
Ind.
5
5
5
5
µA
I
SB
2
CMOS Standby
Current
(CMOS Inputs)
OR
ULB Control
4
5
6
7
8
V
CC
= Max.,
CS
= V
IL
V
IN
0.2V, f = 0;
UB
/
LB
= V
CC
– 0.2V
Note:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency; f = 0 means no input lines change.
CAPACITANCE
(1)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Input/Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
8
10
Unit
pF
pF
9
10
11
12
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/17/00
5
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