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IS61/64WV12816EFALL

IS61/64WV12816EFBLL

128Kx16 HIGH SPEED AYNCHRONOUS

CMOS STATIC RAM with ECC

KEY FEATURES

DESCRIPTION



High-speed access time: 8ns, 10ns, 12ns

Single power supply

– 1.65V-2.2V V

(IS61/64WV12816EFALL)

– 2.4V-3.6V V

(IS61/64WV12816EFBLL)

Error Detection and Correction with optional

ERR1/ERR2 output pin:



ERR1 pin indicates 1-bit error detection and

correction.

ERR2 pin indicates 2-bit error detection

The

ISSI

IS61/64WV12816EFALL/EFBLL are high-speed,

low power, 2M bit static RAMs organized as 128K words by

16 bits. It is fabricated using

ISSI's

high-performance CMOS

technology and implemented ECC function to improve

reliability.

This highly reliable process coupled with innovative circuit

design techniques including ECC (SEC-DED: Single Error

Correcting-Double Error Detecting) yield high-performance

and highly reliable devices.

When CS# is HIGH (deselected), the device assumes a

standby mode at which the power dissipation can be

reduced down with CMOS input levels.

Easy memory expansion is provided by using Chip Enable

and Output Enable inputs. The active LOW Write Enable

(WE#) controls both writing and reading of the memory. A

data byte allows Upper Byte (UB#) and Lower Byte (LB#)

access.

The IS61/64WV12816EFALL/EFBLL are packaged in the

JEDEC standard 48-ball mini BGA (6mm x 8mm), and 44-pin

TSOP (TYPE II)

JANUARY 2021



Three state outputs

Industrial and Automotive temperature support

Lead-free available



FUNCTIONAL BLOCK DIAGRAM

A0 – A17

A16

DECODER

Memory

Lower IO ECC Upper IO ECC

Array

128Kx8 128Kx5 128Kx8 128Kx5

256Kx8 256Kx5 256Kx8 256Kx5

VDD

VSS

ERR1

ERR2

I/O0 – I/O7

I/O8 – I/O15

I/O

DATA

CIRCUIT

ECC

COLUMN I/O

Column I/O

CS#

OE#

WE#

UB#

LB#

ZZ#

CONTROL

CIRCUIT

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can

reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such

applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Integrated Silicon Solution, Inc.-

www.issi.com

Rev. A2

01/11/2021

IS61/64WV12816EFALL

IS61/64WV12816EFBLL

PIN CONFIGURATIONS

48-Ball mini BGA(6mm x 8mm),

(Package Code : B)

48-Ball mini BGA (6mm x 8mm)

(Package Code : B2)

LB#

OE#

LB#

OE#

I/O8

UB#

CS#

I/O0

UB#

CS#

I/O8

I/O9

I/O10

I/O1

I/O2

I/O1

I/O2

I/O10

I/O9

VSS

I/O11

I/O3

VDD

VSS

I/O3

I/O11

VDD

I/O12

A16

I/O4

VSS

VDD

I/O4

A16

I/O12

VSS

I/O14

I/O13

A14

A15

I/O5

I/O6

I/O5

A14

A15

I/O13

I/O14

I/O15

A12

A13

WE#

I/O7

A12

A13

WE#

I/O15

A10

A11

A10

A11

48-Ball mini BGA(6mm x 8mm), ERR1

(Package Code : B3)

48-Ball mini BGA(6mm x 8mm), ERR1, Switched IO

(Package Code : B4)

LB#

OE#

LB#

OE#

I/O8

UB#

CS#

I/O0

UB#

CS#

I/O8

I/O9

I/O10

I/O1

I/O2

I/O1

I/O2

I/O10

I/O9

VSS

I/O11

I/O3

VDD

VSS

I/O3

I/O11

VDD

I/O12

ERR1

A16

I/O4

VSS

VDD

I/O4

ERR1

A16

I/O12

VSS

I/O14

I/O13

A14

A15

I/O5

I/O6

I/O5

A14

A15

I/O13

I/O14

I/O15

A12

A13

WE#

I/O7

A12

A13

WE#

I/O15

A10

A11

A10

A11

Integrated Silicon Solution, Inc.-

www.issi.com

Rev. A2

01/11/2021

IS61/64WV12816EFALL

IS61/64WV12816EFBLL

48-Ball mini BGA(6mm x 8mm), ERR1/2

(Package Code : B5)

LB#

OE#

I/O8

UB#

CS#

I/O0

I/O9

I/O10

I/O1

I/O2

VSS

I/O11

I/O3

VDD

I/O12

ERR1

A16

I/O4

VSS

I/O14

I/O13

A14

A15

I/O5

I/O6

I/O15

ERR2

A12

A13

WE#

I/O7

A10

A11

44-Pin TSOP-II, (Package Code : T)

44-Pin TSOP-II with ERR1, (Package Code : T2)

CS#

I/O0

I/O1

I/O2

I/O3

VDD

VSS

I/O4

I/O5

I/O6

I/O7

WE#

A16

A15

A14

A13

A12

OE#

UB#

LB#

I/O15

I/O14

I/O13

I/O12

VSS

VDD

I/O11

I/O10

I/O9

I/O8

A10

A11

CS#

I/O0

I/O1

I/O2

I/O3

VDD

VSS

I/O4

I/O5

I/O6

I/O7

WE#

A16

A15

A14

A13

A12

OE#

UB#

LB#

I/O15

I/O14

I/O13

I/O12

VSS

VDD

I/O11

I/O10

I/O9

I/O8

ERR1

A10

A11

Integrated Silicon Solution, Inc.-

www.issi.com

Rev. A2

01/11/2021

IS61/64WV12816EFALL

IS61/64WV12816EFBLL

PIN DESCRIPTIONS

A0-A16

I/O0-I/O15

CS#

OE#

WE#

LB#

UB#

ERR1

ERR2

VSS

Address Inputs

Data Inputs/Outputs

Chip Enable Input

Output Enable Input

Write Enable Input

Lower-byte Control

(I/O0-I/O7)

Upper-byte Control

(I/O8-I/O15)

1-bit Error Detection and

Correction Signal

2-bit ERR Detection Signal

No Connection

Power

Ground

Integrated Silicon Solution, Inc.-

www.issi.com

Rev. A2

01/11/2021

IS61/64WV12816EFALL

IS61/64WV12816EFBLL

FUNCTION DESCRIPTION

SRAM is one of random access memories. Each byte or word has an address and can be accessed randomly. SRAM

has three different modes supported. Each function is described below with Truth Table.

STANDBY MODE

Device enters standby mode when deselected (CS# HIGH). The input and output pins (I/O0-15) are placed in a high

impedance state. CMOS input in this mode will maximize saving power.

WRITE MODE

Write operation issues with Chip selected (CS#) and Write Enable (WE#) input LOW. The input and output pins (I/O0-

15) are in data input mode. Output buffers are closed during this time even if OE# is LOW. UB# and LB# enables a

byte write feature. By enabling LB# LOW, data from I/O pins (I/O0 through I/O7) are written into the location specified

on the address pins. And with UB# being LOW, data from I/O pins (I/O8 through I/O15) are written into the location.

READ MODE

Read operation issues with Chip selected (CS# LOW) and Write Enable (WE#) input HIGH. When OE# is LOW, output

buffer turns on to make data output. Any input to I/O pins during READ mode is not permitted. UB# and LB# enables a

byte read feature. By enabling LB# LOW, data from memory appears on I/O0-7. And with UB# being LOW, data from

memory appears on I/O8-15.

In the READ mode, output buffers can be turned off by pulling OE# HIGH. In this mode, internal device operates as

READ but I/Os are in a high impedance state. Since device is in READ mode, active current is used.

ERROR DETECTION AND ERROR CORRECTION



Independent ECC per each byte



detect and correct one bit error per byte or detect 2-bit error per byte

Optional ERR1 output signal indicates 1-bit error detection and correction

Optional ERR2 output signal indicates 2-bit error detection.

Controller can use either ERR1 or ERR2 to monitor ECC event. Unused pins (ERR1 or ERR2) can be left

floating.



Better reliability than parity code schemes which can only detect an error but not correct an error

Backward Compatible: Drop in replacement to current in industry standard devices (without ECC)

ERR1, ERR2 OUTPUT SIGNAL BEHAVIOR

ERR1

High-Z

ERR2

High-Z

DQ pin

Status

Remark

Valid Q No Error

Valid Q 1-Bit Error only

In-Valid Q 2-Bit Error only

1-bit error per byte detected and corrected

No 1-bit error. 2-bit error per byte detected (out of 2 bytes)

In-Valid Q 1-bit & 2-bit error 1-bit error detected and corrected at one byte, and 2-bit error detected at another byte.

Valid D Non-Read

Write operation or Output Disabled

Integrated Silicon Solution, Inc.-

www.issi.com

Rev. A2

01/11/2021

型号	IS64WV12816EFALL-12B2LA3	IS61WV12816EFALL-10BLI	IS61WV12816EFBLL-10B4LI	IS61WV12816EFBLL-10BLI	IS64WV12816EFBLL-10B4LA3	IS61WV12816EFALL-10TLI	IS61WV12816EFBLL-10T2LI	IS64WV12816EFALL-12BLA3	IS64WV12816EFALL-12CT2LA3
描述	Standard SRAM,	Standard SRAM,	Standard SRAM,	Standard SRAM,	Standard SRAM,	Standard SRAM,	Standard SRAM,	Standard SRAM,	Standard SRAM,
Objectid	7248986832	7248986736	7248986744	7248986748	7248986848	7248986738	7248986749	7248986840	7248986841
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown
ECCN代码	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99