ISD3800 DATASHEET
ISD3800
Digital ChipCorder
with
Digital Audio Interface
-1-
Publication Release Date: Aug 23, 2013
Revision 1.0
ISD3800 DATASHEET
TABLE OF CONTENTS
1
2
3
4
GENERAL DESCRIPTION .............................................................................................................. 3
FEATURES ...................................................................................................................................... 3
BLOCK DIAGRAM ........................................................................................................................... 5
PINOUT CONFIGURATION ............................................................................................................ 6
4.1
5
6
48L-LQFP ................................................................................................................................................ 6
PIN DESCRIPTION .......................................................................................................................... 7
ELECTRICAL CHARACTERISTICS .............................................................................................. 11
6.1
O
PERATING
C
ONDITIONS
........................................................................................................................ 11
6.2
DC P
ARAMETERS
................................................................................................................................... 12
6.3
AC P
ARAMETERS
................................................................................................................................... 13
6.3.1
Inputs ............................................................................................................................................. 13
6.3.2
Outputs ........................................................................................................................................... 15
6.3.3
SPI Timing ..................................................................................................................................... 18
6.3.4
I
2
S Timing ...................................................................................................................................... 19
7
8
APPLICATION DIAGRAM .............................................................................................................. 21
PACKAGE SPECIFICATION ......................................................................................................... 23
8.1
48 L
EAD
LQFP(7
X
7
X
1.4
MM FOOTPRINT
2.0
MM
).................................................................................... 23
9
10
ORDERING INFORMATION .......................................................................................................... 24
REVISION HISTORY.................................................................................................................. 25
-2-
Publication Release Date: Aug 23, 2013
Revision 1.0
ISD3800 DATASHEET
1
GENERAL DESCRIPTION
®
The ISD3800 is a digital ChipCorder featuring digital compression, comprehensive memory
management, and integrated analog/digital audio signal paths. The ISD3800 utilizes serial flash
2
memory to provide non-volatile audio playback for a two-chip solution. The ISD3800 provides an I S
digital audio interface, faster digital programming, higher sampling frequency, and a signal path with
SNR 80dB.
2
2
The ISD3800 can take digital audio data via I S or SPI interface. When I S input is selected, it will
replace the analog audio inputs and will support sample rates of 32, 44.1 or 48 kHz depending upon
clock configuration. When SPI interface is chosen, the sample rate of the audio data sent must be one
of the ISD3800 supported sample rates.
The ISD3800 has inbuilt analog audio inputs, analog audio line driver, and speaker driver output.
The analog audio input, Aux-in, has a fixed gain configured by SPI command. Aux-in can directly
feed-through to the analog outputs; it can also mix with the DAC output and then feed-through to the
analog outputs.
Analog outputs are available in two forms: (1) Aux-out is an analog single-ended voltage output; (2)
Class-AB BTL (bridge-tied-load) is an analog differential voltage output. Class-AB BTL delivers 1-watt
output power at V
CCSPK
= 5V.
Class-D PWM direct-drive is also available, which delivers 1-watt output power at V
CCSPK
= 5V.
2
FEATURES
External Memory:
o
The
ISD3800
supports the following flash:
Winbond
25X
EF 30 1X
25Q
EF 40 1X
25P
20 20 1X
Numonyx
25PX
20 71 1X
MXIC
25L / 25V
C2 20 1X
Manufacturer
Family
JEDEC ID
o
25PE
20 80 1X
The addressing ability of ISD3800 is up to 128Mbit, which is 64-minute playback time based
on 8kHz/4bit ADPCM.
o
Inbuilt 3V voltage regulator to provide power source to the external flash memory
Fast Digital Programming
o
Programming rate can go up to 1Mbits/second mainly limited by the flash memory write rate.
Memory Management
o
Store pre-recorded audio (Voice Prompts) using high quality digital compression
o
Use a simple index-based command for playback
o
Execute pre-programmed macro scripts (Voice Macros) designed to control the configuration
of the device and play back Voice Prompts sequences.
Sample Rate
o
Seven sampling frequencies are available for a given master sample rate. For example, the
sampling frequencies of 4, 5.3, 6.4, 8, 12.8, 16 and 32kHz are available when the device is
clocked at a 32kHz master sample rate.
2
o
For I S operation, 32, 44.1 and 48kHz master sample rates are available with playback
sampling frequencies scaling accordingly.
Compression Algorithms
o
For Pre-Recorded Voice Prompts
µ-Law: 6, 7 or 8 bits per sample
Publication Release Date: Aug 23, 2013
Revision 1.0
-3-
ISD3800 DATASHEET
Differential µ-Law: 6, 7 or 8 bits per sample
PCM: 8, 10 or 12 bits per sample
Enhanced ADPCM: 2, 3, 4 or 5 bits per sample
Variable-bit-rate optimized compression. This allows best possible compression given a
metric of SNR and background noise levels.
Oscillator
o
Internal oscillator with internal reference: 2.048 MHz with ±1% deviation
1
o
Internal oscillator with external resistor: 2.048 MHz with ±2% deviation
o
External crystal or clock input
Crystals support standard audio sampling rates of 2.048, 4.096, 8.192, 12.288 and
11.2896MHz
2
o
I S bit clock input
Inputs
o
Aux-in: Analog input with 2-bit gain control configured by SPI command
Outputs
o
PWM: Class-D speaker driver to directly drive an 8Ω speaker or buzzer
Deliver 1-watt output power at
V
CCSPK
= 5V
o
Aux-out: an analog single-ended voltage output
o
Class
-AB BTL: an analog differential voltage output
Deliver 1-watt output power at
V
CCSPK
= 5V
Class-AB BTL can
directly drive an 8Ω speaker or buzzer
Class-AB BTL can
drive an 8Ω speaker or buzzer via an external amplifier
I/Os
o
SPI interface: MISO, MOSI, SCLK, SSB for commands and digital audio data
2
2
2
2
2
o
I S interface: I S_CLK, I S_WS, I S_SDI, I S_SDO for digital audio data
o
8 GPIO pins:
2
4 GPIO pins share with I S
4 GPIO pins share with SPI Interface
GPIO pins can trigger Voice Macro for a pushbutton application
8-bit Volume Control set by SPI command for flexible mixing
Operating Voltage: 2.7 ~ 5.5V
Standby Current: 1uA typical
Package:
o
Green 48L-LQFP
Temperature Options:
o
Industrial: -40C to 85C
1
With ±1% precision 80kohm external resistor.
Publication Release Date: Aug 23, 2013
Revision 1.0
-4-
ISD3800 DATASHEET
3
BLOCK DIAGRAM
Av = 0, 3, 6, 9dB
AUXIN
AUXIN
SUM2
GPIO7 / SDI
GPIO6 / SCK
GPIO5 / WS
GPIO4 / SDO
+
AUX_MUX
I2S
Interface
Digital Signal Path:
Digital Filters
Resampling
Volume Control
DAC
AUXOUT
AUXOUT
PWM
Control
SPK+_MUX
SPK+
De-Compression
SPK-_MUX
SPK-
SCLK
SSB
GPIO1 / MISO
GPIO0 / MOSI
GPIO3 / INTB
GPIO2 / RDY/BSYB
SPI
Interface
Memory Management
and Command
Interpreter
Flash Memory
Controller
Figure 3-1 ISD3800 Block Diagram
FCLK
FCSB
FDI
FDO
-5-
Publication Release Date: Aug 23, 2013
Revision 1.0
