CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1.
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: using a max positive pulse of 6.5V on the SHDN pin, and using
a max negative pulse of -0.8V for all pins.
Analog Specifications
Over recommended operating conditions unless otherwise stated. Parameters with MIN and/or MAX limits are
100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not
production tested.
PARAMETER
End-to-End resistance
W option
U option
End-to-End resistance tolerance
End-to-End Temperature Coefficient
W and U option
W option
U option
R
W
C
W
(Note 13)
Wiper resistance
Wiper capacitance
V
CC
= 3.3V @ +25°C,
wiper current = V
CC
/R
TOTAL
-20
±50
±80
70
25
200
TEST CONDITIONS
MIN
TYP
(Note 3)
10
50
+20
MAX
UNIT
k
k
%
ppm/°C
(Note 13)
ppm/°C
(Note 13)
pF
SYMBOL
R
TOTAL
VOLTAGE DIVIDER MODE
(measured at R
W
i, unloaded; i = 0, 1, 2 or 3)
INL
(Note 8)
DNL
(Note 7)
ZSerror
(Note 5)
Integral non-linearity
Differential non-linearity
Zero-scale error
Monotonic over all tap positions
W option
U option
FSerror
(Note 6)
Full-scale error
W option
U option
V
MATCH
(Note 9)
TC
V
(Note 10)
DCP to DCP matching
Ratiometric temperature coefficient
Any two DCPs at same tap position
DCP register set to 40 hex
-1
-0.5
0
0
-5
-2
-2
±4
1
0.5
-1
-1
1
0.5
5
2
0
0
2
LSB
(Note 4)
LSB
(Note 4)
LSB
(Note 4)
LSB
(Note 4)
LSB
(Note 4)
LSB
(Note 4)
LSB
(Note 4)
ppm/°C
FN6333 Rev 3.00
July 17, 2009
Page 3 of 13
ISL22449
Operating Specifications
Over the recommended operating conditions unless otherwise specified. Parameters with MIN and/or MAX
limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
SYMBOL
I
CC1
PARAMETER
V
CC
Supply Current (volatile
write/read)
V
CC
Supply Current (volatile
write/read)
I
CC2
V
CC
Supply Current ( non-volatile
write/read)
V
CC
Supply Current ( non-volatile
write/read)
I
SB
V
CC
Current (standby)
TEST CONDITIONS
V
CC
= +3.6V, 10k DCP, f
SPI
= 5MHz; (for SPI
active, read and write states)
V
CC
= +3.6V, 50k DCP, f
SPI
= 5MHz; (for SPI
active, read and write states)
V
CC
= +5.5V, 10k DCP, f
SPI
= 5MHz; (for SPI
active, read and write states)
V
CC
= +5.5V, 50k DCP, f
SPI
= 5MHz; (for SPI
active, read and write states)
V
CC
= +5.5V, 10k DCP, SPI interface in
standby state
V
CC
= +5.5V, 50k DCP, SPI interface in
standby state
V
CC
= +3.6V, 10k DCP, SPI interface in
standby state
V
CC
= +3.6V, 50k DCP, SPI interface in
standby state
I
SD
V
CC
Current (shutdown)
V
CC
= +5.5V @ +85°C, SPI interface in
standby state
V
CC
= +5.5V@ +125°C, SPI interface in
standby state
V
CC
= +3.6V @ +85°C, SPI interface in
standby state
V
CC
= +3.6V @ +125°C, SPI interface in
standby state
I
LkgDig
t
WRT
(Note 13)
t
ShdnRec
(Note 13)
Leakage current, at pins SHDN, SCK, Voltage at pin from GND to V
CC
SDI, SDO and CS
DCP wiper response time
SCK falling edge of last bit of DCP data byte
to wiper new position
-1
1.5
1.5
1.5
2.0
0.2
V
CC
above Vpor, to DCP Initial Value
Register recall completed, and SPI Interface
in standby state
3
2.6
MIN
TYP
(Note 3)
MAX
2.5
0.65
4.0
3.0
2.4
525
1.6
350
5
6.5
4
5.5
1
UNIT
mA
mA
mA
mA
mA
µA
mA
µA
µA
µA
µA
µA
µA
µs
µs
µs
V
V/ms
ms
DCP recall time from shutdown mode From rising edge of SHDN signal to wiper
stored position and RH connection
SCK rising edge of last bit of ACR data byte
to wiper stored position and RH connection
Vpor
VccRamp
t
D
Power-on recall voltage
Vcc ramp rate
Power-up delay
Minimum V
CC
at which memory recall occurs
EEPROM SPECIFICATION
EEPROM Endurance
EEPROM Retention
t
WC
(Note 11)
Non-volatile Write cycle time
Temperature
T < +55
°C
1,000,000
50
12
20
Cycles
Years
ms
SERIAL INTERFACE SPECIFICATIONS
V
IL
SHDN, SCK, SDI, and CS input buffer
LOW voltage
-0.3
0.3*V
CC
V
FN6333 Rev 3.00
July 17, 2009
Page 4 of 13
ISL22449
Operating Specifications
Over the recommended operating conditions unless otherwise specified. Parameters with MIN and/or MAX
limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
(Continued)
SYMBOL
V
IH
Hysteresis
V
OL
R
pu
(Note 12)
Cpin
(Note 13)
f
SCK
t
CYC
t
WH
t
WL
t
LEAD
t
LAG
t
SU
t
H
t
RI
t
FI
t
DIS
t
V
t
HO
t
RO
t
FO
t
CS
t
WRT
NOTES:
3. Typical values are for T
A
= +25°C and 3.3V supply voltage.
4. LSB: [V(R
W
)
127
– V(R
W
)
0
]
/
127. V(R
W
)
127
and V(R
W
)
0
are V(R
W
) for the DCP register set to 7F hex and 00 hex respectively. LSB is the
incremental voltage when changing from one tap to an adjacent tap.
5. ZS error = V(RW)
0
/
LSB.
6. FS error = [V(RW)
127
– V
CC
]
/
LSB.
7. DNL = [V(RW)
i
– V(RW)
i-1
]
/
LSB-1, for i = 1 to 127. i is the DCP register setting.
