DATASHEET
ISL45041
TFT-LCD I2C Programmable VCOM Calibrator
The V
COM
voltage of an LCD panel needs to be adjusted to
remove flicker. The ISL45041 part provides a digital interface
to control the sink current output that attaches to an external
voltage divider. The increase in output sink current lowers the
voltage on the external divider, which is applied to an external
V
COM
buffer amplifier. The desired V
COM
setting is loaded from
an external source via a standard 2-wire I
2
C serial interface. At
power-up, the part automatically comes up at the last
programmed EEPROM setting.
An external resistor attaches to the SET pin and sets the
full-scale sink current that determines the lowest voltage of
the external voltage divider.
The ISL45041 is available in an 8 Ld 3mmx3mm TDFN
package with a maximum thickness of 0.8mm for ultra thin
LCD panel design.
An evaluation kit complete with software to control the DCP
from a computer is available. Reference Application Note
AN1275
and “Ordering Information” on
page 2.
FN6189
Rev 6.00
Apr 22, 2016
Features
• 128-step adjustable sink current output
• 2.25V to 3.6V logic supply voltage operating range (2.6V
minimum programming voltage)
• 4.5V to 18V analog supply voltage operating range (10.8V
minimum programming voltage)
• I
2
C interface with addresses 100111x and 100110x
• On-chip 7-Bit EEPROM
• Output adjustment SET pin
• Output guaranteed monotonic over-temperature
• Thin 8 Ld 3mmx3mm DFN (0.8mm max)
• Pb-free (RoHS compliant)
Applications
• LCD panels
Related Literature
•
AN1208
“LCD screens don't flicker - or do they?”
•
AN1275,
“ISL45041EVAL1Z User’s Manual”
V
DD
5
A
VDD
2
SDA
SCL
6
7
I
2
C
INTERFACE
DAC
REGISTERS
ANALOG DCP
AND
CURRENT SINK
Q1
1
OUT
WP
3
7-BIT EEPROM
CURRENT SINK
ISL45041
4
GND
A1
8
SET
FIGURE 1. BLOCK DIAGRAM
FN6189 Rev 6.00
Apr 22, 2016
Page 1 of 8
ISL45041
Pin Configuration
ISL45041
(8 LD TDFN)
TOP VIEW
OUT
AVDD
WP
GND
1
2
3
4
PAD
8
7
6
5
SET
SCL
SDA
VDD
Pin Descriptions
PIN
PIN
NUMBER NAME
1
OUT
TYPE
Output
PULL U/D
FUNCTION
Adjustable Sink Current Output Pin. The current that sinks into the OUT pin is equal to the DAC setting times
the maximum adjustable sink current divided by 128. See SET pin function description for the maximum
adjustable sink current setting.
High-Voltage Analog Supply. Bypass to GND with 0.1µF capacitor.
Pull-Down Write Protect. Active Low. To enable programming, connect to 0.7*V
DD
supply or greater. The WP pin is
designed for static control. It has an internal pull-down current sink. To avoid the possibly overwriting the
EEPROM contents, no frequency above 1Hz should be applied to this input. Care should be taken to avoid
any glitches on the input. When removing or applying mechanical jumpers, always ensure the V
DD
power is
off. A high to low transition on the WP pin results in the register contents being loaded with EEPROM data.
Ground connection
Digital power supply input. Bypass to GND with 0.1µF capacitor.
I
2
C Serial Data Input and Output
I
2
C Clock Input
Maximum Sink Current Adjustment Point. Connect a resistor from SET to GND to set the maximum
adjustable sink current of the OUT pin. The maximum adjustable sink current is equal to (AV
DD
/20) divided
by RSET.
Thermal pad. Electrically connected to GND. Connect to ground plane on PCB to maximize thermal
performance.
2
3
AVDD
WP
Supply
Input
4
5
6
7
8
GND
VDD
SDA
SCL
SET
Supply
Supply
In/Out
Input
Analog
Pad
Power
Ordering Information
PART NUMBER
(Notes
1, 2, 3)
ISL45041IRZ
ISL45041EVAL1Z
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to
TB347
for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for
ISL45041.
For more information on MSL, please see Technical Brief
TB363.
041Z
Evaluation Board
PART
MARKING
TEMP.
RANGE
(°C)
0 to +85
PACKAGE
(Pb-Free)
8 Ld 3x3 TDFN
PKG.
DWG. #
L8.3x3A
FN6189 Rev 6.00
Apr 22, 2016
Page 2 of 8
ISL45041
Absolute Maximum Ratings
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4V
Input Voltages to GND
SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +4V
AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +20V
Output Voltages to GND
OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +A
VDD
ESD Rating
Human Body Model
Device (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . . . . . . . . . . 2kV
Input Pins (SCL, SDA) (Tested per JESD22-A114E) . . . . . . . . . . . . . . 4kV
Thermal Information
Thermal Resistance (Typical)
JA
(°C/W)
JC
(°C/W)
8 Ld TDFN Package (Notes
4, 5).
. . . . . . . .
53
11
Moisture Sensitivity (see Technical Brief
TB363)
All Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 2
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see
TB493
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4.
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief
TB379.
5. For
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER
POWER SUPPLY CHARACTERISTICS
Test Conditions: V
DD
= 3.3V, AV
DD
= 18V, R
SET
= 5kΩ, R1 = 10kΩ, R2 = 10kΩ; (See
Figure 2)
Unless otherwise
specified. Typicals are at T
A
= +25°C. Boldface limits apply across the operating temperature range, 0°C to +85°C.
SYMBOL
TEST CONDITIONS
MIN
(Note
6)
TYP
MAX
(Note
6)
UNITS
V
DD
Supply Range Supporting EEPROM Programming
AV
DD
Supply Range Supporting EEPROM Programming
V
DD
Supply Range for Wide-supply Operation
(not supporting EEPROM programming)
AV
DD
Supply Range for Wide-supply Operation
(not supporting EEPROM programming)
V
DD
Supply Current
AV
DD
Supply Current
DC CHARACTERISTICS
SET Voltage Resolution
SET Differential Nonlinearity
SET Zero-scale Error
SET Full-scale Error
SET Current (R
SET
= 24.9kΩ and AV
DD
= 10V)
SET External Resistance
V
DD
AV
DD
V
DD
AV
DD
2.6V < V
DD
< 3.6V
2.25V < V
DD
< 2.6V
I
DD
I
AVDD
(Note
7)
(Note
8)
2.6
10.8
2.25
4.5
4.5
3.6
18
3.6
18
13
65
38
V
V
V
V
V
µA
µA
SET
VR
SET
DN
SET
ZSE
SET
FSE
ISET
SET
ER
Through R
SET
(Note
11)
To GND, AV
DD
= 18V
To GND, AV
DD
= 4.5V
To GND, AV
DD
= 15V, V
DD
= 3V
V
OUT
> 2.5V (Note
12)
Monotonic Over-temperature
7
7
7
1
3
8
Bits
LSB
LSB
LSB
µA
20
5
2.25
1.0
1:20
8
V
SET
+ 0.5V
13
<10
200
45
200
kΩ
kΩ
kΩ
V/V
µs
V
mV
AV
DD
to SET Voltage Attenuation
OUT Settling Time
OUT Voltage Range
SET Voltage Drift
AVDD to
SET
OUT
ST
V
OUT
SET
VD
(Note
9)
To
0.5
LSB Error Band
(Note
9)
25°C < T
A
< 55°C (Note
9)
FN6189 Rev 6.00
Apr 22, 2016
Page 3 of 8
ISL45041
Electrical Specifications
PARAMETER
SDA, SCL Input Logic High
SDA, SCL Input Logic Low
SDA, SCL Hysteresis
SDA Output Logic High
SDA Output Logic Low
WP Input Logic High
WP Input Logic Low
WP Hysteresis
WP Input Current
I
2
C Timing
SCL Clock Frequency
I
2
C Clock High Time
I
2
C Clock Low Time
I
2
C Spike Rejection Filter Pulse Width
I
2
C Data Set Up Time
I
2
C Data Hold Time
I
2
C SDA, SCL Input Rise Time
I
2
C SDA, SCL Input Fall Time
Test Conditions: V
DD
= 3.3V, AV
DD
= 18V, R
SET
= 5kΩ, R1 = 10kΩ, R2 = 10kΩ; (See
Figure 2)
Unless otherwise
specified. Typicals are at T
A
= +25°C. Boldface limits apply across the operating temperature range, 0°C to +85°C. (Continued)
SYMBOL
I
2
CV
IH
I
2
CV
IL
(Note
9)
VOH
S
VOL
S
V
IH
V
IL
(Note
9)
IL
WPN
0.20
0.14V
DD
35
at 3mA
0.7*V
DD
0.3*V
DD
V
DD
- 0.4
0.4
260
TEST CONDITIONS
MIN
(Note
6)
0.7*V
DD
0.55
TYP
MAX
(Note
6)
UNITS
V
V
mV
V
V
V
V
V
µA
f
SCL
t
SCH
t
SCL
t
DSP
t
SDS
t
SDH
t
ICR
t
ICF
t
BUF
t
STS
t
STH
t
SPS
Cb
C
SDA
C
S
t
W
Dependent on Load (Note
10)
(Note
10)
0
0.6
1.3
0
100
900
20 + 0.1*Cb
20 + 0.1*Cb
200
0.6
0.6
0.6
400
kHz
µs
µs
50
ns
ns
ns
1000
300
ns
ns
µs
µs
µs
µs
I
2
C Bus Free Time Between Stop and Start
I
2
C Repeated Start Condition Set-up
I
2
C Repeated Start Condition Hold
I
2
C Stop Condition Set-up
I
2
C Bus Capacitive Load
SDA Pin Capacitance
SCL Pin Capacitance
EEPROM Write Cycle Time
NOTES:
400
10
10
100
pF
pF
pF
ms
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
7. I
DD
current may increase to 2mA for 45ms or less during each EEPROM programming operation.
8. I
AVDD
current may increase to 1mA for 30ms or less during each EEPROM programming operation.
9. Simulated and Determined via Design and NOT Directly Tested.
10. Simulated and Designed According to I
2
C Specifications.
11. A typical Current of 20µA is Calculated using AV
DD
= 10V and R
SET
= 24.9kΩ. Reference “R
SET
Resistor” in
Figure 3.
12. Minimum value of R
SET
resistor guaranteed when: AV
DD
= 15V, V
DD
= 3.0V and when voltage on the VOUT pin is greater than 2.5V. Reference
Equation 2
on page 5
with Setting = 128.
FN6189 Rev 6.00
Apr 22, 2016
Page 4 of 8
ISL45041
Application Information
This device provides the ability to reduce the flicker of an LCD
panel by adjustment of the V
COM
voltage during production test
and alignment. A 128-step resolution is provided under digital
control, which adjusts the sink current of the output. The output is
connected to an external voltage divider, so that the device will
have the capability to reduce the voltage on the output by
increasing the output sink current.
AVDD
ISL45041
OUT
R
SET
I
OUT
R
2
AVDD
R
1
-
+
R
SET
Resistor
The external R
SET
resistor sets the full-scale sink current, I
SET
maximum, that determines the lowest voltage of the external
voltage divider R
1
and R
2
(Figure
2).
The voltage difference between
the OUT pin and SET pin (Figure
3),
which are also the drain and
source of the output transistor, must be greater than 1.75V. This will
keep the output transistor in its saturation region to maintain linear
operation over the full range of register values. Expected current
settings and 7-bit accuracy occurs when the output MOS transistor is
operating in the saturation region.
Figure 3
shows the internal
connection for the output MOS transistor. The value of the AV
DD
supply sets the voltage at the source of the output transistor. This
voltage is equal to (Setting/128) x (AV
DD
/20). The I
SET
current is
therefore equal to (Setting/128) x (AV
DD
/20 x R
SET
). The drain
voltage is calculated using
Equation 2.
The values of R
1
and R
2
(Equation
2)
should be determined using I
OUT
maximum (setting
equal to 128) so the minimum value of V
OUT
is greater than 1.75V +
AV
DD
/20.
AV
DD
SETTING
-
----------------------------x -----------------
20
128
OUT PIN
AV
DD
= 15V
R
1
VSAT
0.5V
R
2
SET
FIGURE 2. OUTPUT CONNECTION CIRCUIT EXAMPLE
The adjustment of the output is provided by the 2-wire I
2
C serial
interface.
Expected Output Voltage
The ISL45041 provides an output sink current, which lowers the
voltage on the external voltage divider (V
COM
output voltage).
Equations 1
and
2
can be used to calculate the output current
(I
OUT)
and output voltage (V
OUT
) values. The setting is the register
value +1 with a value between 1 and 128.
AV
DD
Setting
-
-
I
OUT
= --------------------
x
--------------------------
20
R
SET
128
R
1
R
2
Setting
-
-
-
V
OUT
=
--------------------
AV
DD
1
– --------------------
x
--------------------------
20
R
SET
128
R
1
+
R
2
(EQ. 1)
AVDD
R
SET
SET PIN
FIGURE 3. OUTPUT CONNECTION CIRCUIT EXAMPLE
Ramp-Up of the VDD Power Supply
The ramp-up from 10% V
DD
to 90% V
DD
level must be achieved
in 10ms or less to ensure that the EEPROM and power-on-reset
circuits are synchronized and the correct value is read from the
EEPROM Memory.
(EQ. 2)
Table 1
gives the calculated value of V
OUT
using the resistor values
of: R
SET
= 24.9kΩ, R
1
= 200kΩ, R
2
= 243kΩ and AV
DD
= 10V.
TABLE 1.
SETTING VALUE
1
10
20
30
40
50
60
70
80
90
100
110
128
V
OUT
(V)
5.468
5.313
5.141
4.969
4.797
4.625
4.453
4.281
4.109
3.936
3.764
3.592
3.282
Power Supply Sequence
The recommended power supply sequencing is shown in
Figure 3.
When applying power, VDD should be applied before or
at the same time as AVDD. The minimum time for t
VS
is 0µs.
When removing power, the sequence of VDD and AVDD is not
important.
V
DD
A
VDD
t
VS
FIGURE 3. POWER SUPPLY SEQUENCE
Do not remove VDD or AVDD within 100ms of the start of the
EEPROM programming cycle. Removing power before the
EEPROM programming cycle is completed may result in
corrupted data in the EEPROM.
FN6189 Rev 6.00
Apr 22, 2016
Page 5 of 8
