Laser Diode Driver with APC Amplifier for Printers
ISL58115
The ISL58115 is a high-performance laser driver that provides
controlled current to grounded laser diodes. A bias current is
summed with the switched current at the IOUT output, allowing
the user to optimize laser diode performance.
Output switched current flows when the LVDS signal DATA is high.
The output current returns to the fixed-threshold value when
DATA is low. Complete I
OUT
shut-off is achieved by holding the
CHPEN low, which will override all other control pins.
A fast settling APC amplifier connects directly to the monitor
diode. The ISL58115 does not exhibit any time-dependent droop
since the calibration gain is stored as a digital number.
Features
• Voltage-controlled Output Current Source
• Very Few External Components Needed
• Internal LVDS Termination Resistors
• 300MHz Switching
• Up to 110mA Output Current
• Rise Time < 500ps
• Fall Time < 500ps
• APC Loop for Write Power Control
• Fast Settling APC Amplifier
• Single +5V Supply (±10%)
• Disable Feature for Power-Up Protection and Conserving Power
• Zero Droop
PKG.
DWG. #
L24.4x5B
Ordering Information
PART NUMBER
(Notes 1, 2)
ISL58115CRZ-T13
NOTES:
1. Please refer to
TB347
for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-
free material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is
RoHS compliant and compatible with both SnPb and Pb-free
soldering operations). Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
PART
MARKING
58115 CRZ
PACKAGE
Tape & Reel
(Pb-free)
24 Ld QFN
• Pb-Free (RoHS compliant)
Load Configuration
• Common-cathode LD, Common-anode PD
IOUT PDIN
GND
Applications
• Laser Printer Applications
• Laser Diode Current Switching
July 29, 2013
FN6671.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Copyright Intersil Americas LLC 2010, 2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL58115
Pin Configuration
ISL58115
(24 LD QFN)
TOP VIEW
21 CALB
20 HPSB
19 NC
18 GND
17 VCC
THERMAL
THERMAL
PAD
16 IOUT
15 VCC
14 VCC
13 PDIN
RBIAS 10
CHPEN 8
IVOUT 12
RSET 11
RPS 9
24 GND
23 NC
22 VC
NC 1
DATA 2
DATAB 3
GND 4
DIS 5
NC 6
NC 7
Pin Descriptions
PIN
NAME
DATA
DATAB
GND
DIS
NC
CHPEN
RPS
RBIAS
RSET
IVOUT
PDIN
VCC
IOUT
HPSB
CALB
VC
Thermal
Pad
PIN
NUMBER
2
3
4, 18, 24
5
1, 6, 7, 19,
23
8
9
10
11
12
13
14, 15, 17
16
20
21
22
-
O
I
I
I
O
O
I
I
I
I
I
I/O
I
I
TYPE
LVDS
LVDS
Ground
Digital
No connect
Digital
Analog
Analog
Analog
Analog
Analog
Power
Analog
TLL
TTL
Analog
DESCRIPTION
Input data to control Laser Switching Control
Input data to control Laser Switching Control
Ground
Disable output current
No connect
Chip Enable; Pull High to Enable
External resistor sets the Hsync detection power
Resistors set bias threshold current. See “Applications Information” on page 7 for more details
Bandgap derived internal reference
Calibrate channel with an external trimpot to GND
Adjust the IV amplifier gain
Photo Diode input to the IV amplifier
Supply Voltage
Laser Current Output
Hsync Power Select Enable; Active Low. During HPSB is low AND Hsync signal from photo
detector is low, the output current is set by RPS
Samples the laser power for APC; Active Low
Voltage Controlling Laser Switching Current; 0V to 2V input for 0% to 100% output
Exposed Thermal Pad should be soldered to GND
NOTE: Pins with the same name are not necessary internally connected together. LDD pins must not be used for connecting together external components
or features.
2
FN6671.1
July 29, 2013
ISL58115
Absolute Maximum Ratings
(T
A
= +25°C)
Voltages Applied to:
V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6.0V
All Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to V
CC
+ 0.5V
I
OUT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to V
CC
LVDS Max Current Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
ESD Rating
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 3kV
Charged Device Model (Tested per JESD22-C110D) . . . . . . . . . . . .1.5kV
Machine Model (Tested per JESD22-A115B) . . . . . . . . . . . . . . . . . . 200V
Latch Up (Tested per JESD78B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA
Recommended Operating Conditions
Thermal Resistance (Typical, Notes 3, 4)
θ
JA
(°C/W)
24 Ld QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
42
Operating Ambient Temperature Range . . . . . . . . . . . . . . . . 0°C to +85°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
3.
θ
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
4. For
θ
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise
noted, all tests are at the specified temperature and are pulsed tests, therefore: T
J
= T
C
= T
A
Electrical Specifications
PARAMETER
V
CC
ISdis
IS2
V
LO
V
HI
I
LO
I
HI
V
SHUT
V
LVDS
V
CMR
V
C
R
Termination
V
CC
= 5.0V, DIS = Lo, T
A
= +25°C, R
SET
= 3.0kΩ, unless otherwise indicated.
CONDITIONS
MIN
(Note 5)
4.5
DIS = SLPEN = HPSB = Hi
DIS = Hi
All TTL inputs
All TTL inputs
All TTL inputs
All TTL inputs
2.5
Differential, with Vcm = 1.25V
300mV
P-P
0.2
0.3
180
0.2
2.2
2.6
2.8
-20
-10
1
2.9
TYP
5.0
0.3
22
MAX
(Note 5)
5.5
1.0
31
1.2
UNIT
V
mA
mA
V
V
µA
µA
V
V
V
V
Ω
DESCRIPTION
Supply Voltage
Supply Current (Disabled)
Supply Current (Standby)
Low Voltage Threshold
High Voltage Threshold
Input Low Current
Input High Current
VCC Shut Down Voltage
LVDS Input Level
LVDS Common Mode Voltage Range
Control Voltage
Internal LVDS Termination Resistor
Laser Amplifier Output
PARAMETER
I
OUT
IOUT
SW-max
IOUT
BIAS-max
I
OFF
FREQ
OP
IOUT
PSRR
t
R-IOUT
t
F-IOUT
OUTENx_t
on
V
CC
= 5.0V, DIS = Lo, T
A
= +25°C, R
SET
= 3.0kΩ, unless otherwise indicated.
CONDITIONS
MIN
(Note 5)
TYP
MAX
(Note 5)
UNIT
DESCRIPTION
Switched Output Current
Bias Output Current
Output Off Current
Operating Frequency
I
OUT
Supply Sensitivity
I
OUT
Rise Time
I
OUT
Fall Time
I
OUT
on Propagation Delay
VC = 2.6V
R
BIAS
= 1kΩ
DIS pin set to HIGH
I
OUT
= maximum switch current
I
OUT
= 20mA, V
CC
= 5V ±10%
10% to 90%; typical LD for printer
90% to 10%; typical LD for printer
DATAx crossing to I
OUT
at 50% of final value
75
20
-75
200
81
35
0
+75
mA
mA
µA
MHz
13
0.5
0.7
5
7
%/V
ns
ns
ns
3
FN6671.1
July 29, 2013
ISL58115
Laser Amplifier Output
PARAMETER
VC
BW
V
CC
= 5.0V, DIS = Lo, T
A
= +25°C, R
SET
= 3.0kΩ, unless otherwise indicated.
CONDITIONS
MIN
(Note 5)
TYP
14
V
CC
= 5.0V, DIS = Lo, T
A
= +25°C, R
SET
= 3.0kΩ, unless otherwise indicated.
CONDITIONS
0V to 2V step of VC
External resistor RIV = 500Ω
MIN
(Note 5)
TYP
7.5
3.1
MAX
(Note 5)
UNIT
µs
kΩ
MAX
(Note 5)
UNIT
MHz
DESCRIPTION
Bandwidth of VC
APC Electrical Specifications
PARAMETER
t
APC-50
IVgain
DESCRIPTION
APC Response Time
IV Amplifier Gain
NOTE:
5. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
Timing Diagram
CHPEN
DIS
VC
CALB
DATA(LVDS)
HPSB
SET BY
RPS
I
OUT
RISES TO
ITS VC DEFINED
VALUE USING
THE LAST
CALIBRATION
GAIN SETTING IN
<1µs
FIXED BIAS
LEVEL
SET BY R
BIAS
I
OUT
OFF
OFF
4
FN6671.1
July 29, 2013
ISL58115
I
OUT
Control
CHPEN
DIS
DATA
CALB
HPSB
I
OUT
COMMENTS
POWER-DOWN (SLEEP MODE)
0
x
x
x
x
OFF
CHPEN is slow to enable
STANDBY (FULL STANDBY CURRENT, NO I
OUTS
)
1
1
x
x
x
OFF
Full standby current, no I
OUT
NORMAL DRIVE
1
1
1
Hsync POWER
1
0
x
1
0
Hsync power
Output current defined by RPS
0
0
0
x
x
1
1
0
1
1
1
1
ON, BIAS ONLY
ON, CAL to level set by VC
ON
INVALID LOGIC COMBINATION
1
0
x
1
x
INVALID
NOTE: DATA1 and DATA2: 1 implies DATA>DATAB, 0 implies DATA<DATAB
5
FN6671.1
July 29, 2013
