ISL6225
SIGNS
NEW DE
E D F OR
T:
MMEND REPLACEMEN
ECO
N OT R
N DED
COMME SL6227
RE
I
DATASHEET
FN9049
Rev 7.00
December 28, 2004
Dual Mobile-Friendly PWM Controller with DDR Memory Option
The ISL6225 dual PWM controller delivers high efficiency and
tight regulation from two voltage regulating synchronous buck
DC/DC converters. The ISL6225 PWM power supply controller
was designed especially for DDR DRAM, SDRAM, and graphic
chipset applications in high performance desknote PCs,
notebook PCs, sub-notebook PCs, and PDAs.
Automatic mode selection of constant-frequency synchronous
rectification at heavy load, and hysteretic diode-emulation at
light load, assure high efficiency over a wide range of
conditions. The hysteretic mode of operation can be disabled
separately on each PWM converter if constant-frequency
continuous-conduction operation is desired for all load levels.
Efficiency is further enhanced by using the lower MOSFET
r
DS(ON)
as the current sense element.
Voltage-feed-forward ramp modulation, average current mode
control, and internal feedback compensation provide fast
response to input voltage and output load transients. Input
current ripple is minimized by channel to channel PWM
phase shift of 0°, 90°, or 180° determined by input voltage
and status of the DDR pin.
The ISL6225 can control two independent output voltages
adjustable from 0.9V to 5.5V or, by activating the DDR pin,
transform into a complete DDR memory power supply
solution. In DDR mode, CH2 output voltage VTT tracks CH1
output voltage VDDQ. CH2 output can both source and sink
current, an essential power supply feature for DDR memory
systems. The reference voltage VREF required by DDR
memory is generated as well.
In dual power supply applications the ISL6225 monitors the
output voltage of both CH1 and CH2. An independent
PGOOD (power good) signal is asserted for each channel
after the soft-start sequence has completed, and the output
voltage is within ±10% of the set point. In DDR mode CH1
generates the only PGOOD signal.
Built-in overvoltage protection prevents the output from
going above 115% of the set point by holding the lower
MOSFET on and the upper MOSFET off. When the output
voltage decays below the overvoltage threshold, normal
operation automatically resumes. Once the soft-start
sequence has completed, under-voltage protection may
latch the ISL6225 off if either output drops below 75% of its
set point value.
Adjustable overcurrent protection (OCP) monitors the
voltage drop across the r
DS(ON)
of the lower MOSFET. If
more precise current-sensing is required, an external current
sense resistor may be used.
Features
• Provides regulated output voltage in the range of 0.9V-5.5V
- High efficiency over wide load range
- Synchronous buck converter with hysteretic operation at
light load
- Inhibit Hysteretic mode on one, or both channels
• Complete DDR memory power solution
- VTT tracks VDDQ/2
- VDDQ/2 buffered reference output
• No current-sense resistor required
- Uses MOSFET r
DS(ON)
- Optional current-sense resistor for precision overcurrent
• Under-voltage lock-out on V
CC
pin
• Dual input voltage mode operation
- Operates directly from battery 5V to 24V input
- Operates from 3.3V or 5V system rail
- VCC from 5V only
• Excellent dynamic response
- Combined voltage feed-forward and average current
mode control
• Power-good signal for each channel
• 300kHz switching frequency
- 180° channel to channel phase operation for reduced input
ripple when not in DDR mode
- 0° channel to channel phase operation in DDR mode for
reduced channel interference
- 90° channel to channel phase operation for reduced input
ripple in DDR mode when VIN is at GND.
• Pb-Free Available (RoHS Compliant)
Applications
• Mobile PCs
• PDAs
• Hand-held portable instruments
Ordering Information
PART NUMBER
ISL6225CA
ISL6225CAZ (Note 1)
ISL6225CAZA (Note 1)
TEMP. (°C)
-10 to 85
-10 to 85
-10 to 85
PACKAGE
28 Ld SSOP
PKG.
DWG. #
M28.15
28 Ld SSOP (Pb-free) M28.15
28 Ld SSOP (Pb-free) M28.15
NOTES:
1. Intersil Pb-free products employ special Pb-free material sets; molding
compounds/die attach materials and 100% matte tin plate termination
finish, which are RoHS compliant and compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
2. Add “-T” for Tape and Reel.
FN9049 Rev 7.00
December 28, 2004
Page 1 of 19
ISL6225
Pinout
ISL6225
SSOP-28
TOP VIEW
GND
LGATE1
PGND1
PHASE1
UGATE1
BOOT1
ISEN1
EN1
VOUT1
1
2
3
4
5
6
7
8
9
28 VCC
27 LGATE2
26 PGND2
25 PHASE2
24 UGATE2
23 BOOT2
22 ISEN2
21 EN2
20 VOUT2
19 VSEN2
18 OCSET2
17 SOFT2
16 PG2/REF
15 PG1
VSEN1 10
OCSET1 11
SOFT1 12
DDR 13
VIN 14
FN9049 Rev 7.00
December 28, 2004
Page 2 of 19
ISL6225
Absolute Maximum Ratings
Bias Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+ 6.5V
Input Voltage, V
IN
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +27.0V
PHASE, UGATE Voltage . . . . . . . . . . . . . . GND-5V (Note 3) to 33V
BOOT, ISEN Voltage . . . . . . . . . . . . . . . . . . . . GND-0.3V to +33.0V
BOOT with respect to PHASE . . . . . . . . . . . . . . . . . . . . . . . . .+ 6.5V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to V
CC
+ 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Thermal Information
Thermal Resistance (Typical, Note 4)
JA
(°C/W)
SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
78
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(SSOP - Lead Tips Only)
Recommended Operating Conditions
Bias Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.0V
5%
Input Voltage, V
IN
. . . . . . . . . . . . . . . . . . . . . . . . . . . +5.0V to +24.0V
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . .-10°C to 85°C
Junction Temperature Range. . . . . . . . . . . . . . . . . . .-10°C to 125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
3. 200ns transient.
4.
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
PARAMETER
V
CC
SUPPLY
Bias Current
Shut-down Current
V
CC
UVLO
Rising V
CC
Threshold
Falling V
CC
Threshold
V
IN
Input Voltage Pin Current (Sink)
Input Voltage Pin Current (Source)
Shut-down Current
OSCILLATOR
PWM1 Oscillator Frequency
Ramp Amplitude, pk-pk
Ramp Amplitude, pk-pk
Ramp Offset
Ramp/V
IN
Gain
Ramp/V
IN
Gain
REFERENCE AND SOFT-START
Internal Reference Voltage
Reference Voltage Accuracy
Soft-Start Current During Start-up
Soft-Start Complete Threshold
Recommended Operating Conditions, Unless Otherwise Noted.
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
I
CC
I
CCSN
LGATEx, UGATEx Open, VSENx forced above
regulation point, DDR = 0, VIN > 5V
-
-
2.2
-
3.2
30
mA
A
V
CCU
V
CCD
4.3
4.1
4.65
4.35
4.75
4.45
V
V
I
VIN
I
VINO
I
VINS
10
-
-
-
-15
-
30
-30
1
A
A
A
F
C
V
R1
V
R2
V
ROFF
G
RB1
G
RB2
V
IN
= 16V, by design
V
IN
= 5V, by design
By design
V
IN
3V,
by design
1V
IN
3V,
by design
255
-
-
-
-
-
300
2
1.25
0.5
125
250
345
-
-
-
-
-
kHz
V
V
V
mV/V
mV/V
V
REF
-
-1.0
0.9
-
-5
1.5
-
+1.0
-
-
V
%
A
V
I
SOFT
V
ST
By design
-
-
FN9049 Rev 7.00
December 28, 2004
Page 3 of 19
ISL6225
Electrical Specifications
PARAMETER
PWM CONVERTERS
Load Regulation
VSEN pin bias current
V
OUT
pin input impedance
Undervoltage Shut-Down Level
Overvoltage Shut-Down
GATE DRIVERS
Upper Drive Pull-Up Resistance
Upper Drive Pull-Down Resistance
Lower Drive Pull-Up Resistance
Lower Drive Pull-Down Resistance
POWER GOOD AND CONTROL FUNCTIONS
Power Good Lower Threshold
Power Good Higher Threshold
PGOODx Leakage Current
PGOODx Voltage Low
EN - Low (Off)
EN - High (On)
CCM Enforced (Hysteretic Operation
Inhibited)
Automatic CCM/Hysteretic Operation Enabled
DDR - Low (Off)
DDR - High (On)
DDR REF Output Voltage
DDR REF Output Current
V
DDREF
I
DDREF
DDR = 1, I
REF
= 0...10mA
DDR = 1. Guaranteed by design.
VOUTX pulled low
VOUTX connected to the output
V
PG-
V
PG+
I
PGLKG
V
PGOOD
Fraction of the set point; ~3s noise filter
Fraction of the set point; ~3s noise filter.
Guaranteed by design.
V
PULLUP
= 5.5V
I
PGOOD
= -4mA
-13
12
-
-
-
2.5
-
0.9
-
2.5
0.99*
V
OC2
-
-
-
-
0.5
-
-
-
-
-
-
V
OC2
10
-7
16
1
0.85
0.8
-
0.1
-
0.8
-
1.01*
V
OC2
16
%
%
A
V
V
V
V
V
V
V
V
mA
R
2UGPUP
R
2UGPDN
R
2LGPUP
R
2LGPDN
V
CC
= 4.5V
V
CC
= 4.5V
V
CC
= 4.5V
V
CC
= 4.5V
-
-
-
-
8
3.2
8
1.8
15
5
15
3
I
VSEN
I
VOUT
V
UVL
V
OVP1
0.0mA < I
VOUT1
< 5.0A; 5.0V < V
BATT
< 24.0V
By design
V
OUT
= 5V
Fraction of the set point; ~2s noise filter
Fraction of the set point; ~2s noise filter
-2.0
50
40
70
110
-
80
55
-
-
+2.0
120
65
85
130
%
nA
k
%
%
Recommended Operating Conditions, Unless Otherwise Noted.
(Continued)
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
FN9049 Rev 7.00
December 28, 2004
Page 4 of 19
ISL6225
Functional Pin Description
GND (Pin 1)
Signal ground for the IC.
SOFT1, SOFT2 (Pin 12, 17)
These pins provide soft-start function for their respective
controllers. When the chip is enabled, the regulated 5A
pull-up current source charges the capacitor connected from
the pin to ground. The output voltage of the converter follows
the ramping voltage on the SOFT pin.
LGATE1, LGATE2 (Pin 2, 27)
These are outputs of the lower MOSFET drivers.
PGND1, PGND2 (Pin 3, 26)
These pins provide the return connection for lower gate
drivers. These pins are connected to sources of the lower
MOSFETs of their respective converters.
DDR (Pin 13)
This pin, when high, transforms dual channel chip into
complete DDR memory solution. The OCSET2 pin becomes
an input to provide the required tracking function. The
channel synchronization is changed from out-of-phase to in-
phase. The PG2/REF pin becomes the output of the VDDQ/
2 buffered voltage that is used as a reference voltage by the
second channel.
PHASE1, PHASE2 (Pin 4, 25)
The PHASE1 and PHASE2 points are the junction points of
the upper MOSFET sources, output filter inductors, and
lower MOSFET drains. Connect these pins to the respective
converter’s upper MOSFET source.
VIN (Pin 14)
Provides battery voltage to the oscillator for feed-forward
rejection of the input voltage variation.
When connected to ground via 100k resistor while the
DDR pin is high, this pin commands the out-of-phase 90
o
channels synchronization for reduced inter-channel
interference.
UGATE1, UGATE2 (Pin 5, 24)
These pins provide the gate drive for the upper MOSFETs.
BOOT1, BOOT2 (Pin 6, 23)
These pins power the upper MOSFET drivers of the PWM
converter. Connect this pin to the junction of the bootstrap
capacitor with the cathode of the bootstrap diode. Anode of
the bootstrap diode is connected to the VCC pin.
PG1 (Pin 15)
PGOOD1 is an open drain output used to indicate the status
of the output voltage. This pin is pulled low when the first
channel output is not within ±10% of the set value.
ISEN1, ISEN2 (Pin 7, 22)
These pins are used to monitor the voltage drop across the
lower MOSFET for current feedback and overcurrent
protection. For precise current detection these inputs can be
connected to the optional current sense resistors placed in
series with the source of the lower MOSFETs.
PG2/REF (Pin 16)
This pin has a double function depending on the mode the
chip is operating. When the chip is used as a dual channel
PWM controller (DDR = 0), the pin provides a PGOOD2
function for the second channel. The pin is pulled low when
the second channel output is not within ±10% of the set value.
In DDR mode (DDR = 1), this pin serves as an output of the
buffer amplifier that provides VDDQ/2 reference voltage
applied to the OCSET2 pin.
EN1, EN2 (Pin 8, 21)
These pins enable operation of the respective converter
when high. When both pins are low, the chip is disabled and
only low leakage current <1A is taken from V
CC
and V
IN
.
These pins are to be connected together and switched at the
same time.
OCSET2 (Pin 18)
In a dual channel application (DDR = 0), a resistor from this
pin to ground sets the overcurrent threshold for the second
controller.
In the DDR application (DDR = 1), this pin sets the output
voltage of the buffer amplifier and the second controller and
should be connected to the center point of a divider from the
VDDQ output.
VOUT1, VOUT2 (Pin 9, 20)
These pins when connected to the converters’ respective
outputs provide the output voltage inside the chip to reduce
output voltage excursion during HYS/PWM transition. When
connected to ground, these pins command forced
converters operate in continuous conduction mode at all
load levels.
VSEN1, VSEN2 (Pin 10, 19)
These pins are connected to the resistive dividers that set
the desired output voltage. The PGOOD, UVP, and OVP
circuits use this signal to report output voltage status.
VCC (Pin 28)
This pin powers the controller.
OCSET1 (Pin 11)
A resistor from this pin to ground sets the overcurrent
threshold for the first controller.
FN9049 Rev 7.00
December 28, 2004
Page 5 of 19
FPGA/CPLD
