DATASHEET
ISL6310
Two-Phase Buck PWM Controller with High Current Integrated MOSFET Drivers
The ISL6310 is a two-phase PWM control IC with integrated
MOSFET drivers. It provides a precision voltage regulation
system for multiple applications including, but not limited to,
high current low voltage point-of-load converters, embedded
applications and other general purpose low voltage medium
to high current applications. The integration of power
MOSFET drivers into the controller IC marks a departure
from the separate PWM controller and driver configuration of
previous multi-phase product families. By reducing the
number of external parts, this integration allows for a cost
and space saving power management solution.
Output voltage can be programmed using the on-chip DAC
or an external precision reference. A two bit code programs
the DAC reference to one of 4 possible values (0.6V, 0.9V,
1.2V and 1.5V). A unity gain, differential amplifier is provided
for remote voltage sensing, compensating for any potential
difference between remote and local grounds. The output
voltage can also be offset through the use of single external
resistor. An optional droop function is also implemented and
can be disabled for applications having less stringent output
voltage variation requirements or experiencing less severe
step loads.
A unique feature of the ISL6310 is the combined use of both
DCR and r
DS(ON)
current sensing. Load line voltage
positioning and overcurrent protection are accomplished
through continuous inductor DCR current sensing, while
r
DS(ON)
current sensing is used for accurate channel-current
balance. Using both methods of current sampling utilizes the
best advantages of each technique.
Protection features of this controller IC include a set of
sophisticated overvoltage and overcurrent protection.
Overvoltage results in the converter turning the lower
MOSFETs ON to clamp the rising output voltage and protect
the load. An OVP output is also provided to drive an optional
crowbar device. The overcurrent protection level is set
through a single external resistor. Other protection features
include protection against an open circuit on the remote
sensing inputs. Combined, these features provide advanced
protection for the output load.
FN9209
Rev 4.00
August 7, 2008
Features
• Integrated Multi-Phase Power Conversion
- 1 or 2-Phase Operation
• Precision Output Voltage Regulation
- Differential Remote Voltage Sensing
- ±0.8% System Accuracy Over-Temperature
(for REF = 0.6V and 0.9V)
- ±0.5% System Accuracy Over-Temperature
(for REF=1.2V and 1.5V)
- Usable for Output Voltages not Exceeding 2.3V
- Adjustable Reference-Voltage Offset
• Precision Channel Current Sharing
- Uses Loss-Less r
DS(ON)
Current Sampling
• Optional Load Line (Droop) Programming
- Uses Loss-Less Inductor DCR Current Sampling
• Variable Gate-Drive Bias - 5V to 12V
• Internal or External Reference Voltage Setting
- On-Chip Adjustable Fixed DAC Reference Voltage with
2-bit Logic Input Selects from Four Fixed Reference
Voltages (0.6V, 0.9V, 1.2V, 1.5V)
- Reference can be Changed Dynamically
- Can use an External Voltage Reference
• Overcurrent Protection
• Multi-tiered Overvoltage Protection
- OVP Pin to Drive Optional Crowbar Device
• Selectable Operation Frequency up to 1.5MHz Per Phase
• Digital Soft-Start
• Capable of Start-up in a Pre-Biased Load
• Pb-Free (RoHS Compliant)
Applications
• High Current DDR/Chipset core voltage regulators
• High Current, Low voltage DC/DC converters
• High Current, Low voltage FPGA/ASIC DC/DC converters
FN9209 Rev 4.00
August 7, 2008
Page 1 of 27
ISL6310
Ordering Information
PART
NUMBER
ISL6310CRZ* (Note)
ISL6310IRZ* (Note)
ISL6310EVAL1Z
PART
MARKING
ISL6310 CRZ
ISL6310 IRZ
Evaluation Platform (Pb-free)
TEMP. RANGE
(°C)
0 to +70
-40 to +85
PACKAGE
(Pb-Free)
32 Ld 5x5 QFN
32 Ld 5x5 QFN
PKG.
DWG. #
L32.5x5
L32.5x5
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations).
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
Pinout
ISL6310
(32 LD QFN)
TOP VIEW
UGATE1
25
24 BOOT1
23 PHASE1
22 OVP
33
GND
21 REF1
20 ENLL
19 PHASE2
18 BOOT2
17 UGATE2
9
OCSET
10
ICOMP
11
DROOP
12
ISUM
13
IREF
14
LGATE2
15
PVCC
16
ISEN2
LGATE1
27
PGOOD
ISEN1
26
REF0
30
DAC
2PH
32
REF
OFST
VCC
COMP
FB
VDIFF
RGND
VSEN
1
2
3
4
5
6
7
8
31
FS
29
28
FN9209 Rev 4.00
August 7, 2008
Page 2 of 27
ISL6310
Block Diagram
ICOMP DROOP
OCSET
PGOOD
OVP
ENLL
ISEN AMP
ISUM
IREF
100µA
OC
0.66V
POWER-ON
RESET
VCC
PVCC
RGND
VSEN
+1V
BOOT1
UGATE1
GATE
CONTROL
LOGIC
SHOOT-
THROUGH
PROTECTION
SOFT-START
x1
x1
AND
FAULT LOGIC
PHASE1
VDIFF
LGATE1
UVP
0.2V
FS
OVP
CLOCK AND
SAWTOOTH
GENERATOR
OVP
BOOT2
UGATE2
GATE
CONTROL
LOGIC
SHOOT-
THROUGH
PROTECTION
+150mV
x 0.82
PWM1
PHASE2
LGATE2
REF1
DAC
REF0
DAC
PWM2
PHASE 2
DETECT
2PH
REF
FB
E/A
CHANNEL
CURRENT
BALANCE
1
N
COMP
OFFSET
OFST
CHANNEL
CURRENT
SENSE
ISEN1
ISEN2
GND
FN9209 Rev 4.00
August 7, 2008
Page 3 of 27
ISL6310
Typical Application - ISL6310
+12V
VDIFF
FB
COMP
PVCC
BOOT1
VSEN
RGND
UGATE1
PHASE1
ISEN1
LGATE1
+5V
2PH
VCC
OFST
FS
DAC
ISL6310
REF
LOAD
REF1
REF0
OVP
PGOOD
+12V
+12V
GND
BOOT2
UGATE2
PHASE2
ISEN2
LGATE2
ICOMP
ISUM
ENLL
IREF
DROOP
OCSET
FN9209 Rev 4.00
August 7, 2008
Page 4 of 27
ISL6310
Absolute Maximum Ratings
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V
Supply Voltage, PVCC . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +15V
Absolute Boot Voltage, V
BOOT
. . . . . . . . GND - 0.3V to GND + 36V
Phase Voltage, V
PHASE
. . . . . . . . GND - 0.3V to 15V (PVCC = 12)
GND - 8V (<400ns, 20µJ) to 24V (<200ns, V
BOOT-PHASE
= 12V)
Upper Gate Voltage, V
UGATE
. . . . V
PHASE
- 0.3V to V
BOOT
+ 0.3V
V
PHASE
- 3.5V (<100ns Pulse Width, 2µJ) to V
BOOT
+ 0.3V
Lower Gate Voltage, V
LGATE
. . . . . . . . GND - 0.3V to PVCC + 0.3V
GND - 5V (<100ns Pulse Width, 2µJ) to PVCC+ 0.3V
Input, Output, or I/O Voltage . . . . . . . . . GND - 0.3V to VCC + 0.3V
Thermal Information
Thermal Resistance
JA
(°C/W)
JC
(°C/W)
QFN Package (Notes 1, 2) . . . . . . . . . .
35
5
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V
5%
PVCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . +5V to 12V
5%
Ambient Temperature (ISL6310CR, ISL6310CRZ) . . . 0°C to +70°C
Ambient Temperature (ISL6310IR, ISL6310IRZ) . . .-40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1.
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Specified. Parameters with MIN and/or MAX limits are
100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are
not production tested.
TEST CONDITIONS
MIN
TYP
MAX
UNITS
PARAMETER
BIAS SUPPLY AND INTERNAL OSCILLATOR
Input Bias Supply Current
Gate Drive Bias Current
VCC POR (Power-On Reset) Threshold
I
VCC
; ENLL = high
I
PVCC
; ENLL = high, all gate outputs open,
Fsw = 250kHz
VCC Rising
VCC Falling
-
-
4.25
3.75
4.25
3.75
-
-
15
1.5
4.38
3.88
4.38
3.88
1.50
66.6
20
3.0
4.50
4.00
4.50
4.00
-
-
mA
mA
V
V
V
V
V
%
PVCC POR (Power-On Reset) Threshold
PVCC Rising
PVCC Falling
Oscillator Ramp Amplitude (Note 3)
Maximum Duty Cycle (Note 3)
CONTROL THRESHOLDS
ENLL Rising Threshold
ENLL Hysteresis
COMP Shutdown Threshold
REFERENCE AND DAC
System Accuracy (DAC = 0.6V, 0.9V)
System Accuracy (DAC = 1.2V, 1.50V)
DAC Input Low Voltage (REF0, REF1)
DAC Input High Voltage (REF0, REF1)
External Reference
OFS Sink Current Accuracy (Negative Offset)
OFS Source Current Accuracy (Positive Offset)
V
P-P
-
-
COMP Falling
0.25
0.66
100
0.35
-
-
0.5
V
mV
V
DROOP connected to IREF
DROOP connected to IREF
-0.8
-0.5
-
0.8
0.6
-
-
-
-
-
50.0
50.0
0.8
0.5
0.4
-
1.75
52.5
52.5
%
%
V
V
V
µA
µA
R
OFS
= 30kfrom OFS to VCC
R
OFS
= 10kfrom OFS to GND
47.5
47.5
FN9209 Rev 4.00
August 7, 2008
Page 5 of 27
