CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1.
θ
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For
θ
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER
Test Conditions: V
CC
= 5V, T
J
= 0°C to +85°C, Unless Otherwise Specified
TEST CONDITIONS
MIN
TYP
MAX
UNITS
BIAS SUPPLY AND INTERNAL OSCILLATOR
Input Bias Supply Current
VCC POR (Power-On Reset) Threshold
I
VCC
; ENLL = high
VCC Rising
VCC Falling
PVCC POR (Power-On Reset) Threshold
PVCC Rising
PVCC Falling
Switching Frequency (per channel)
T
J
= +25°C to +85°C
T
J
= -40°C
Oscillator Ramp Amplitude
Maximum Duty Cycle (Note 3)
CONTROL THRESHOLDS
ENLL Rising Threshold
ENLL Falling Threshold
REFERENCE AND DAC
System Accuracy
T
J
= -40°C to +85°C
DAC Input Low Voltage
DAC Input High Voltage
DAC Input Pull-Up Current
ERROR AMPLIFIER
DC Gain (Note 3)
Gain-Bandwidth Product (Note 3)
Slew Rate (Note 3)
Maximum Output Voltage
Minimum Output Voltage
OVERCURRENT PROTECTION
Overcurrent Trip Level
72
95
115
μA
R
L
= 10k to ground
C
L
= 100pF, R
L
= 10k to ground
C
L
= 100pF, Load =
±400μA
Load = 1mA
Load = -1mA
-
-
-
3.90
-
96
20
8
4.20
0.80
-
-
-
-
0.90
dB
MHz
V/μs
V
V
VIDx = 0V
-1
-1.5
-
0.8
-
-
-
-
-
45
1
1.5
0.4
-
-
%
%
V
V
μA
-
-
0.645
0.567
-
-
V
mV
V
P-P
-
4.2
3.7
-
-
189
166
-
-
4
4.4
3.9
4.3
3.3
222
205
1.33
67
6
4.6
4.1
-
-
255
241
-
-
mA
V
V
V
V
kHz
kHz
V
%
4
FN9222.1
July 18, 2007
ISL6315
Electrical Specifications
PARAMETER
PROTECTION
Overvoltage Threshold while IC Disabled
VRM9.0 configuration
Hammer and VRM10.0 configurations
Overvoltage Threshold
Overvoltage Hysteresis
SWITCHING TIME
UGATE Rise Time (Note 3)
LGATE Rise Time (Note 3)
UGATE Fall Time (Note 3)
LGATE Fall Time (Note 3)
UGATE Turn-On Non-overlap (Note 3)
LGATE Turn-On Non-overlap (Note 3)
OUTPUT
Upper Drive Source Resistance
Upper Drive Sink Resistance
Lower Drive Source Resistance
Lower Drive Sink Resistance
NOTES:
3. Limits should be considered typical and are not production tested.
100mA Source Current
100mA Sink Current
100mA Source Current
100mA Sink Current
-
-
-
-
1.0
1.0
1.0
0.4
2.5
2.5
2.5
1.0
Ω
Ω
Ω
Ω
t
RUGATE;
V
VCC
= 5V, 3nF Load
t
RLGATE;
V
VCC
= 5V, 3nF Load
t
FUGATE;
V
VCC
= 5V, 3nF Load
t
FLGATE;
V
VCC
= 5V, 3nF Load
t
PDHUGATE
; V
VCC
= 5V, 3nF Load
t
PDHLGATE
; V
VCC
= 5V, 3nF Load
-
-
-
-
-
-
8
8
8
4
8
8
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
FB Rising
1.90
1.60
-
-
1.95
1.65
VID
+200mV
100
2.00
1.70
-
-
V
V
V
mV
Test Conditions: V
CC
= 5V, T
J
= 0°C to +85°C, Unless Otherwise Specified
(Continued)
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Timing Diagram
t
PDHUGATE
t
RUGATE
t
FUGATE
UGATE
LGATE
t
FLGATE
t
PDHLGATE
t
RLGATE
Functional Pin Description
VCC (Pin 8)
Bias supply for the IC’s small-signal circuitry. Connect this
pin to a 5V supply and locally decouple using a quality 0.1μF
ceramic capacitor.
GND and PGND (Pins 25 and 14)
Connect these pins to the circuit ground using the shortest
possible paths. All internal small-signal circuitry is
referenced to the GND pin. LGATE drive is referenced to the
PGND pin.
PVCC (Pin 16)
Power supply pin for the MOSFET drives. Connect this pin to
a 5V supply and locally decouple using a quality 1μF
ceramic capacitor.
VID0-4 (Pins 2, 1, 24-22)
Voltage identification inputs from microprocessor. These pins
respond to TTL logic thresholds. The ISL6315 decodes the
VID inputs to establish the output voltage; see VID Tables for
correspondence between DAC codes and output voltage
settings. These pins are internally pulled high, to
approximately 1.2V, by 40μA (typically) internal current
