DATASHEET
ISL6520B
Single Synchronous Buck Pulse-Width Modulation (PWM) Controller
The ISL6520B makes simple work out of implementing a
complete control scheme for a DC/DC stepdown converter.
Designed to drive N-channel MOSFETs in a synchronous
buck topology, the ISL6520B integrates the control, output
adjustment and monitoring functions into a single 8 Lead
package.
The ISL6520B provides simple, single feedback loop,
voltage-mode control with fast transient response. The
output voltage can be precisely regulated to as low as 0.8V,
with a maximum tolerance of
1.5%
over-temperature and
line voltage variations. A fixed frequency oscillator reduces
design complexity, while balancing typical application cost
and efficiency.
The error amplifier features a 15MHz gain-bandwidth
product and 8V/s slew rate which enables high converter
bandwidth for fast transient performance. The resulting
PWM duty cycles range from 0% to 100%.
FN9083
Rev 3.00
Jul 23, 2007
Features
• Operates from +5V Input
• 0.8V to V
IN
Output Range
- 0.8V Internal Reference
- ±1.5% Over Line Voltage and Temperature
• Drives N-Channel MOSFETs
• Simple Single-Loop Control Design
- Voltage-Mode PWM Control
• Fast Transient Response
- High-Bandwidth Error Amplifier
- Full 0% to 100% Duty Cycle
• Small Converter Size
- 300kHz Fixed Frequency Oscillator
- Internal Soft Start
- 8 Ld SOIC or 16Ld 4mmx4mm QFN
• QFN Package:
- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat
No Leads - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
• Pb-free Plus Anneal Available (RoHS compliant)
Ordering Information
PART
NUMBER
ISL6520BCB*
PART
MARKING
6520 BCB
TEMP.
RANGE
(°C)
PACKAGE
PKG.
DWG. #
M8.15
M8.15
0 to +70 8 Ld SOIC
ISL6520BCBZ* 6520 BCBZ 0 to +70 8 Ld SOIC
(Note)
(Pb-free)
ISL6520BCR*
65 20BCR
0 to +70 16 Ld 4x4 QFN L16.4x4
Applications
• Power Supplies for Microprocessors
- PCs
- Embedded Controllers
• Subsystem Power Supplies
- PCI/AGP/GTL+ Buses
- ACPI Power Control
- SSTL-2 and DDR SDRAM Bus Termination Supply
• Cable Modems, Set-Top Boxes, and DSL Modems
• DSP and Core Communications Processor Supplies
• Memory Supplies
• Personal Computer Peripherals
• Industrial Power Supplies
• 5V-Input DC/DC Regulators
• Low-Voltage Distributed Power Supplies
ISL6520BCRZ* 65 20BCRZ 0 to +70 16 Ld 4x4 QFN L16.4x4
(Note)
(Pb-free)
ISL6520BIR*
65 20BIR
-40 to +85 16 Ld 4x4 QFN L16.4x4
ISL6520BIRZ* 65 20BIRZ -40 to +85 16 Ld 4x4 QFN L16.4x4
(Note)
(Pb-free)
ISL6520EVAL1 Evaluation Board
*Add “-T” suffix for tape and reel. Please refer to TB347 for details
on reel specifications.
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN9083 Rev 3.00
Jul 23, 2007
Page 1 of 11
ISL6520B
Pinouts
ISL6520B
(8 LD SOIC)
TOP VIEW
BOOT 1
UGATE 2
GND 3
LGATE 4
8 PHASE
7 COMP/SD
6 FB
5 VCC
BOOT
UGATE
GND
NC
1
2
3
4
5
LGATE
6
NC
7
VCC
8
NC
ISL6520B
(16 LD QFN)
TOP VIEW
PHASE
14
NC
NC
NC
13
12
NC
11
COMP/SD
10
NC
9
FB
16
15
Block Diagram
VCC
POR AND
SOFTSTART
BOOT
UGATE
PHASE
+
0.8V
ERROR
AMP
+
PWM
COMPARATOR
+
INHIBIT
-
-
-
GATE
CONTROL
LOGIC
PWM
VCC
FB
COMP/SD
20A
OSCILLATOR
FIXED 300kHz
GND
LGATE
Typical Application
5V
C
DCPL
R
PULLUP
VCC
5
COMP/SD
SHUTDOWN
R
F
C
I
C
F
6
FB
3
GND
1
2
ISL6520B
8
4
BOOT
C
BOOT
UGATE
PHASE
LGATE
Q
L
Q
U
L
OUT
V
OUT
D
BOOT
V
IN
C
HF
C
BULK
7
C
OUT
R
OFFSET
R
S
FN9083 Rev 3.00
Jul 23, 2007
Page 2 of 11
ISL6520B
Absolute Maximum Ratings
Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V
Absolute Boot Voltage, V
BOOT
. . . . . . . . . . . . . . . . . . . . . . . +15.0V
Upper Driver Supply Voltage, V
BOOT
- V
PHASE
. . . . . . . . 7.0V (DC)
8.0V (<10ns Pulse Width, 10J)
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Thermal Information
Thermal Resistance
JA
(°C/W)
JC
(°C/W)
SOIC Package (Note 1) . . . . . . . . . . . .
95
N/A
QFN Package (Notes 2, 3). . . . . . . . . .
45
7
Maximum Junction Temperature
(Plastic Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . -65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±10%
Ambient Temperature Range - ISL6520BC . . . . . . . . . 0°C to +70°C
Junction Temperature Range. . . . . . . . . . . . . . . . . .-40°C to +125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1.
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2.
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
3. For
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER
VCC SUPPLY CURRENT
Nominal Supply
POWER-ON RESET
Rising VCC POR Threshold
VCC POR Threshold Hysteresis
OSCILLATOR
Frequency
Recommended Operating Conditions, Unless Otherwise Noted.
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
I
VCC
2.6
3.2
3.8
mA
POR
4.19
-
4.30
0.25
4.50
-
V
V
f
OSC
V
OSC
ISL6520BC, VCC = 5V
ISL6520BI, VCC = 5V
250
230
-
300
300
1.5
340
340
-
kHz
kHz
V
P-P
Ramp Amplitude
REFERENCE
Reference Voltage Tolerance
ISL6520BC
ISL6520BI
-1.5
-2.5
-
-
+1.5
+2.5
%
%
V
Nominal Reference Voltage
ERROR AMPLIFIER
DC Gain
Gain-Bandwidth Product
Slew Rate
GATE DRIVERS
Upper Gate Source Current
Upper Gate Sink Current
Lower Gate Source Current
Lower Gate Sink Current
DISABLE
Disable Threshold
NOTE:
V
REF
0.800
-
(Note 4)
GBWP
SR
(Note 4)
(Note 4)
-
-
-
88
15
8
-
-
-
dB
MHz
V/s
I
UGATE-SRC
V
BOOT
- V
PHASE
= 5V, V
UGATE
= 4V
I
UGATE-SNK
I
LGATE-SRC
V
VCC
= 5V, V
LGATE
= 4V
I
LGATE-SNK
-
-
-
-
-1
1
-1
2
-
-
-
-
A
A
A
A
V
DISABLE
-
0.8
-
V
4. Limits should be considered typical and are not production tested
FN9083 Rev 3.00
Jul 23, 2007
Page 3 of 11
ISL6520B
Functional Pin Description
VCC
This pin provides the bias supply for the ISL6520B, as well
as the lower MOSFET’s gate. Connect a well-decoupled 5V
supply to this pin.
Functional Description
Initialization
The ISL6520B automatically initializes upon receipt of power.
The Power-On Reset (POR) function continually monitors the
bias voltage at the VCC pin. The POR function initiates the soft
start operation.
FB
This pin is the inverting input of the internal error amplifier.
Use this pin, in combination with the COMP/SD pin, to
compensate the voltage-control feedback loop of the
converter.
Soft Start
The ISL6520B is held in reset with both UGATE and LGATE
driven to ground until the POR threshold on VCC has been
reached and the COMP/SD pin has been pulled above 0.8V. If
COMP is not actively pulled high following POR the internal
20A current sink will hold COMP/SD low and the device will
remain in reset. COMP/SD can either be statically tied to VCC
through a pullup resistor or driven high through a resistor to
terminate reset. The recommended range of resistor values to
use as the pullup resistor is between 50k and 100k.
Following reset the ISL6520B provides a 1024 clock cycle
settling period (~3.4ms) prior to initiating softstart. At the
conclusion of the settling period the COMP/SD pin is driven
to 0.8V for 24 clock cycles (~75s) to discharge the
compensation network. Soft start of the regulated output is
generated by imposing an internal offset on the FB pin which
ramps down from 0.8V to 0V over the next 2048 clock cycles
(~6.8ms). Total time from end of reset to completion of soft-start
is 10.2ms.
Pulling COMP/SD below 0.8V or VCC dropping below
minimum POR initiates another reset.
GND
This pin represents the signal and power ground for the IC.
Tie this pin to the ground island/plane through the lowest
impedance connection available.
PHASE
Connect this pin to the upper MOSFET’s source.
UGATE
Connect this pin to the upper MOSFET’s gate. This pin
provides the PWM-controlled gate drive for the upper
MOSFET. This pin is also monitored by the adaptive shoot-
through protection circuitry to determine when the upper
MOSFET has turned off.
BOOT
This pin provides ground referenced bias voltage to the
upper MOSFET driver. A bootstrap circuit is used to create a
voltage suitable to drive a logic-level N-channel MOSFET.
COMP/SD
This pin is the output of the error amplifier. Use this pin, in
combination with the FB pin, to compensate the voltage-
control feedback loop of the converter.
Pulling COMP/SD to a level below 0.8V disables the
controller. Disabling the ISL6520B causes the oscillator to
stop, the LGATE and UGATE outputs to be held low, and the
softstart circuitry to re-arm. The COMP/SD pin must be
pulled above 0.8V to terminate shutdown. This may be done
through a pullup resistor tied between VCC and COMP/SD.
The recommended range of resistor values to use as the pullup
resistor is between 50k and 100k.
V
COMP/SD
1V/DIV.
V
OUT
500mV/DIV.
TIME (2ms/DIV.)
LGATE
Connect this pin to the lower MOSFET’s gate. This pin
provides the PWM-controlled gate drive for the lower
MOSFET. This pin is also monitored by the adaptive shoot-
through protection circuitry to determine when the lower
MOSFET has turned off.
FIGURE 1. SOFT START INTERVAL
Current Sinking
The ISL6520B incorporates a MOSFET shoot-through
protection method which allows a converter to sink current
as well as source current. Care should be exercised when
designing a converter with the ISL6520B when it is known
that the converter may sink current.
When the converter is sinking current, it is behaving as a
boost converter that is regulating it’s input voltage. This
means that the converter is boosting current into the V
CC
FN9083 Rev 3.00
Jul 23, 2007
Page 4 of 11
ISL6520B
rail, which supplies the bias voltage to the ISL6520B. If there
is nowhere for this current to go, such as to other distributed
loads on the V
CC
rail, through a voltage limiting protection
device, or other methods, the capacitance on the V
CC
bus
will absorb the current. This situation will allow voltage level
of the V
CC
rail to increase. If the voltage level of the rail is
boosted to a level that exceeds the maximum voltage rating
of the ISL6520B, then the IC will experience an irreversible
failure and the converter will no longer be operational.
Ensuring that there is a path for the current to follow other
than the capacitance on the rail will prevent this failure
mode.
as close as practical to the BOOT and PHASE pins. All
components used for feedback compensation should be
located as close to the IC a practical.
BOOT
C
BOOT
D
1
+V
IN
Q
1
L
O
V
OUT
C
O
LOAD
V
OUT
C
O
V
OUT
R
3
R
1
FB
ISL6520B
PHASE
VCC
+5V
Q
2
C
VCC
GND
Application Guidelines
Layout Considerations
As in any high frequency switching converter, layout is very
important. Switching current from one power device to another
can generate voltage transients across the impedances of the
interconnecting bond wires and circuit traces. These
interconnecting impedances should be minimized by using
wide, short printed circuit traces. The critical components
should be located as close together as possible, using ground
plane construction or single point grounding.
V
IN
FIGURE 3. PRINTED CIRCUIT BOARD SMALL SIGNAL
LAYOUT GUIDELINES
Feedback Compensation
Figure 4 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V
OUT
) is regulated to the Reference voltage level. The
error amplifier (Error Amp) output (V
E/A
) is compared with
the oscillator (OSC) triangular wave to provide a
pulse-width modulated (PWM) wave with an amplitude of
V
IN
at the PHASE node. The PWM wave is smoothed by the
output filter (L
O
and C
O
).
OSC
DRIVER
V
IN
L
O
DRIVER
PHASE
PWM
COMPARATOR
V
OSC
ISL6520B
UGATE
PHASE
Q
2
Q
1
L
O
V
OUT
-
LGATE
C
O
LOAD
C
IN
+
Z
FB
RETURN
V
E/A
+
ESR
(PARASITIC)
FIGURE 2. PRINTED CIRCUIT BOARD POWER AND
GROUND PLANES OR ISLANDS
-
Z
IN
REFERENCE
Figure 2 shows the critical power components of the converter.
To minimize the voltage overshoot, the interconnecting wires
indicated by heavy lines should be part of a ground or power
plane in a printed circuit board. The components shown in
Figure 2 should be located as close together as possible.
Please note that the capacitors C
IN
and C
O
may each
represent numerous physical capacitors. Locate the ISL6520B
within 3 inches of the MOSFETs, Q
1
and Q
2
. The circuit traces
for the MOSFETs’ gate and source connections from the
ISL6520B must be sized to handle up to 1A peak current.
Figure 3 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Minimize any leakage
current paths on the COMP/SD pin and locate the resistor,
R
OSCET
close to the COMP/SD pin because the internal
current source is only 20A. Provide local V
CC
decoupling
between VCC and GND pins. Locate the capacitor, C
BOOT
ERROR
AMP
DETAILED COMPENSATION COMPONENTS
C
2
C
1
R
2
Z
FB
Z
IN
C
3
COMP/SD
-
+
ISL6520B
REFERENCE
FIGURE 4. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
FN9083 Rev 3.00
Jul 23, 2007
Page 5 of 11
