®
ISL6549
Data Sheet
September 22, 2006
FN9168.2
Single 12V Input Supply Dual Regulator —
Synchronous Rectified Buck PWM and
Linear Power Controller
The ISL6549 provides the power control and protection for
two output voltages in high-performance applications. The
dual-output controller drives two N-Channel MOSFETs in a
synchronous rectified buck converter topology and one
N-Channel MOSFET in a linear configuration. The controller is
ideal for applications where regulation of both the processing
unit and memory supplies is required.
The synchronous rectified buck converter incorporates
simple, single feedback loop, voltage-mode control with fast
transient response. Both the switching regulator and linear
regulator provide a maximum static regulation tolerance of
±
1% over line, load, and temperature ranges. Each output is
user-adjustable by means of external resistors.
An integrated soft-start feature brings both supplies into
regulation in a controlled manner. Each output is monitored
via the FB pins for undervoltage events. If either output drops
below 75% of the nominal output level, both converters are
shut off and go into retry mode.
The ISL6549 is available in a 14 Ld SOIC package,
16 Ld QSOP, or 16 Ld 4x4 QFN packages.
Features
• Single 12V bias supply (no 5V supply is required)
• Provides two regulated voltages
- One synchronous rectified buck PWM controller
- One linear controller
• Both controllers drive low cost N-Channel MOSFETs
• Small converter size
- Adjustable frequency 150kHz to 1MHz
- Small external component count
• Excellent output voltage regulation
- Both outputs: ±1% over temperature
• 12V down conversion
• PWM and linear output voltage range: down to 0.8V
• Simple single-loop voltage-mode PWM control design
• Fast PWM converter transient response
- High-bandwidth error amplifier
• Undervoltage fault monitoring on both outputs
• Pb-free plus anneal available (RoHS compliant)
Applications
• Processor and memory supplies
• ASIC power supplies
• Embedded processor and I/O supplies
• DSP supplies
Related Literature
• Technical Brief TB363
Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)
Ordering Information
PART NUMBER
ISL6549CB
ISL6549CBZ (Note)
ISL6549CR
ISL6549CRZ (Note)
ISL6549CA
ISL6549CAZ (Note)
ISL6549CAZA (Note)
ISL6549IBZ (Note)
ISL6549IRZ (Note)
ISL6549IAZ (Note)
ISL6549LOW-EVAL1
ISL6549HI-EVAL1
Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets, molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
PART MARKING
ISL6549CB
6549CBZ
ISL6549CR
6549CRZ
ISL6549CA
6549CAZ
6549CAZ
6549IBZ
6549IRZ
6549IAZ
Evaluation Board 1-5A
Evaluation Board up to 20A
TEMP. RANGE (°C)
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
-40 to 85
-40 to 85
-40 to 85
14 Ld SOIC
14 Ld SOIC (Pb-free)
16 Ld 4x4 QFN
16 Ld 4x4 QFN (Pb-free)
16 Ld QSOP
16 Ld QSOP (Pb-free)
16 Ld QSOP (Pb-free)
14 Ld SOIC (Pb-free)
16 Ld 4x4 QFN (Pb-free)
16 Ld QSOP (Pb-free)
PACKAGE
PKG. DWG. #
M14.15
M14.15
L16.4x4
L16.4x4
M16.15A
M16.15A
M16.15A
M14.15
L16.4x4
M16.15A
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL6549
Pinouts
ISL6549 (SOIC)
TOP VIEW
ISL6549 (QFN)
TOP VIEW
FS_DIS
PHASE
UGATE
BOOT
ISL6549 (QSOP)
TOP VIEW
BOOT 1
FS_DIS 2
COMP 3
FB 4
LDO_DR 5
LDO_FB 6
GND 7
14 UGATE
13 PHASE
12 PGND
11 LGATE
10 PVCC5
9 VCC5
8 VCC12
16
COMP
FB
LDO_DR
LDO_FB
1
2
3
4
5
AGND
15
14
13
12
PGND
LGATE
PVCC5
VCC5
BOOT 1
FS_DIS 2
COMP 3
FB 4
LDO_DR 5
LDO_FB 6
AGND 7
DGND 8
16 UGATE
15 PHASE
14 PGND
13 LGATE
12 PVCC5
11 VCC5
10 VCC12
9 VCC12
METAL
GND
PAD
(BOTTOM)
11
10
9
6
DGND
7
VCC12
8
VCC12
VCC5
Block Diagram
VCC12
POWER-ON
VOLTAGE
REFERENCE
RESET (POR)
5V
REGULATOR
PVCC5
LDO_FB
0.80V
0.60V
RESTART
SOFT-START
BOOT
LDO_DR
UGATE
EA2
INHIBIT
SOFT-START
DIS
GATE
LOGIC
PWM
DIS
EA1
COMP
LGATE
PHASE
FS_DIS
OSCILLATOR
PGND
GND
UV1
UV2
FB
COMP
2
FN9168.2
September 22, 2006
ISL6549
Simplified Power System Diagram
+V
IN1
+12V
+V
IN2
Q1
Q3
V
OUT2
+
LINEAR
CONTROLLER
PWM
CONTROLLER
+
V
OUT1
Q2
ISL6549
Typical Application Schematic
+V
IN1
+12V
C
BP12
PVCC5
VCC12
+
BOOT
C
BOOT
UGATE
Q3
LDO_DR
PHASE
Q2
Q1
L
OUT
V
OUT1
+
C
VIN1
C
BP
+V
IN2
C
VIN2
+
C
BP5
VCC5
V
OUT2
LDO_FB
+
C
OUT2
LGATE
C
OUT1
ISL6549
FB
FS_DIS
COMP
GND
PGND
3
FN9168.2
September 22, 2006
ISL6549
Absolute Maximum Ratings
VCC12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +14V
PVCC5, VCC5 . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +7V
VCC5 (if used with external supply). . . . . . . . . . . GND - 0.3V to +6V
BOOT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +27V
PHASE. . . . . . . . . . . . . . . . . . . . . . . . V
BOOT
- 7V to V
BOOT
+ 0.3V
V
BOOT
- V
PHASE
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7V
UGATE. . . . . . . . . . . . . . . . . . . . . . V
PHASE
- 0.3V to V
BOOT
+ 0.3V
LGATE . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to PVCC5 + 0.3V
LDO_DR . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VCC12 + 0.3V
FB, LDO_FB, COMP, FS_DIS . . . . . . . GND - 0.3V to VCC5 + 0.3V
ESD Classification
Human Body Model (Per JESD22-A114C) . . . . . . . . . . . . . . Class 2
Machine Model (Per EIA/JESD22-A115-A) . . . . . . . . . . . . . .Class B
Charge Device Model (Per JESD22-C101C). . . . . . . . . . . . Class IV
Thermal Information
Thermal Resistance
θ
JA
(°C/W)
θ
JC
(°C/W)
SOIC Package (Note 1) . . . . . . . . . . . .
105
N/A
QFN Package (Notes 2, 3). . . . . . . . . .
52
14
QSOP Package (Note 1) . . . . . . . . . . .
110
N/A
Maximum Junction Temperature (Plastic Package) . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . -65°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . +300°C
(SOIC - Lead Tips Only)
Recommended Operating Conditions
External Supply Voltage on VCC5 . . . . . . . . . . . . . . . . . . +5.0V ±5%
Supply Voltage on VCC12 . . . . . . . . . . . . . . . . . . . . . . . +12V ±10%
Ambient Temperature Range (C). . . . . . . . . . . . . . . . . . 0°C to 70°C
Ambient Temperature Range (I) . . . . . . . . . . . . . . . . -40°C to +85°
Junction Temperature Range. . . . . . . . . . . . . . . . . . . 0°C to +125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1.
θ
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2.
θ
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
3. For
θ
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Recommended Operating Conditions, unless otherwise noted. VCC12 = 12V
Temperature = 0 to +70°C (typical = +25°C) for Commercial; Temperature = -40 to + 85°C (typical = +25°C) for
Industrial. Refer to Block Diagram, Simplified Power System Diagram, and Typical Application Schematic.
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
PARAMETER
VCC SUPPLY CURRENT
Nominal Supply Current VCC12 (disabled)
Nominal Supply Current VCC5 (disabled)
Nominal Supply Current VCC12
(includes PVCC5 current)
Nominal Supply Current VCC5
Maximum PVCC5 Current Available (Note 5)
VCC12 to PVCC5 Current Limit (Note 5)
PVCC5 Voltage
I
CC12 dis
I
CC5 dis
I
CC12
I
CC5
I
PVCC5
I
PVCC5CL
V
PVCC5
UGATE, LGATE and LDO_DR open;
FS_DIS = GND
UGATE, LGATE and LDO_DR open;
FS_DIS = GND (Note 4)
UGATE, LGATE and LDO_DR open;
F
OSC
= 620kHz
UGATE, LGATE and LDO_DR open;
F
OSC
= 620kHz
2
5
12
4
100
150
3
7.5
18
6
mA
mA
mA
mA
mA
mA
ISL6549C; No external load
ISL6549I; No external load
4.95
4.85
5.25
5.25
5.8
5.8
V
POWER-ON RESET
Rising VCC5 Threshold
Falling VCC5 Threshold
Rising VCC12 Threshold
Falling VCC12 Threshold
OSCILLATOR AND SOFT-START
Switching Frequency
F
OSC
ISL6549C; R
FS_DIS
= 45.3kΩ
ISL6549I; R
FS_DIS
= 45.3kΩ
540
525
620
620
700
700
kHz
kHz
VCC12 = 12V
VCC12 = 12V
VCC5 = 5V
VCC5 = 5V
3.7
3.3
8.8
7.0
4.2
3.8
9.5
7.5
4.5
4.1
10.0
8.0
V
V
V
V
4
FN9168.2
September 22, 2006
ISL6549
Electrical Specifications
Recommended Operating Conditions, unless otherwise noted. VCC12 = 12V
Temperature = 0 to +70°C (typical = +25°C) for Commercial; Temperature = -40 to + 85°C (typical = +25°C) for
Industrial. Refer to Block Diagram, Simplified Power System Diagram, and Typical Application Schematic.
(Continued)
SYMBOL
DV
OSC
T
SS
F
OSC
= 620kHz
TEST CONDITIONS
MIN
TYP
1.5
6.8
MAX
UNITS
V
ms
PARAMETER
Sawtooth Amplitude (Note 6)
Soft-Start Interval
REFERENCE VOLTAGE
Reference Voltage
V
REF
ISL6549C; For Error Amp 1 and 2
ISL6549I; For Error Amp 1 and 2
0.792
0.788
0.8
0.8
0.808
0.812
V
V
PWM CONTROLLER ERROR AMPLIFIER
DC Gain (Note 6)
Gain-Bandwidth Product (Note 6)
Slew Rate (Note 6)
FB Input Current
COMP High Output Voltage
COMP Low Output Voltage
COMP High Output, Source Current
Undervoltage Level (V
FB
/V
REF
)
PWM CONTROLLER GATE DRIVERS
UGATE Maximum Voltage
LGATE Maximum Voltage
UGATE and LGATE Minimum Voltage
UGATE Source Output Impedance
UGATE Sink Output Impedance
LGATE Source Output Impedance
LGATE Sink Output Impedance
LINEAR REGULATOR (LDO_DR)
DC Gain (Note 6)
Gain-Bandwidth Product (Note 6)
Slew Rate (Note 6)
LDO_FB Input Current
LDO_DR High Output Voltage
LDO_DR Low Output Voltage
LDO_DR High Output Source Current
LDO_DR Low Output Sink Current
Undervoltage Level (V
LDO_FB
/V
REF
)
NOTES:
4. Current in VCC5 is actually higher disabled, due to extra current required to pull down against the FS_DIS pin. VCC12 current is lower disabled.
5. Guaranteed by design, not production tested. Exceeding the maximum current from PVCC5 may result in degraded performance and unsafe
operation.
6. Guaranteed by design, not production tested.
Gain
GBWP
SR
⎜I
I
⎜
V
OUT
High
V
OUT
Low
I
OUT
High
I
OUT
Low
V
UV
Percent of Nominal
70
V
OUT
= 2.0V
R
L
= 10K, C
L
= 10pF
R
L
= 10K, C
L
= 10pF
R
L
= 10K, C
L
= 10pF
V
LDO_FB
= 0.8V
VCC12 = 12V
100
2
6
0.1
11.0
0.0
2.0
0.5
75
80
1.0
11.5
0.5
dB
MHz
V/µs
µA
V
V
mA
mA
%
V
HUGATE
V
HLGATE
V
LGATE
R
DS(ON)
R
DS(ON)
R
DS(ON)
R
DS(ON)
VCC12 = 12V; PHASE = 12V
VCC12 = 12V; based on PVCC5 voltage
VCC12 = 12V; PHASE = 0V
VCC12 = 12V; I
GATE
= 100mA
VCC12 = 12V; I
GATE
= 100mA
VCC12 = 12V; I
GATE
= 100mA
VCC12 = 12V; I
GATE
= 100mA
17
17.5
5.25
0
0.8
0.7
0.8
0.4
18
6
0.5
V
V
Ω
Ω
Ω
Ω
GBWP
SR
⎜I
I
⎜
V
OUT
High
V
OUT
Low
I
OUT
High
V
UV
70
R
L
= 10K, C
L
= 10pF
R
L
= 10K, C
L
= 10pF
R
L
= 10K, C
L
= 10pF
V
FB
= 0.8V
96
20
8
0.1
4.8
0.6
-2.8
75
80
1.0
dB
MHz
V/µs
µA
V
V
mA
%
5
FN9168.2
September 22, 2006
