DATASHEET
ISL6617
PWM Doubler with Phase Shedding Function and Output Monitoring Feature
The ISL6617 utilizes Intersil’s proprietary Phase
Doubler scheme to modulate two-phase power trains
with single PWM input. It doubles the number of
phases that Intersil’s multi-phase controllers ISL63xx
can support. When the enable pin (EN_PH_SYNC) is
pulled low, the PWM input is pulled high. This simplifies
the phase shedding implementation for some Intersil
controllers (VR10, VR11, VR11.1, and VR12 family)
that can disable the respective and higher phase(s) by
pulling the respective PWM line high.
The ISL6617 is designed to minimize the number of
analog signals that interface between the controller
and drivers in high phase count scalable applications.
The common COMP signal, which is usually seen in
conventional cascaded configuration, is not required;
this improves noise immunity and simplifies the layout.
Furthermore, the ISL6617 provides low part count and
low cost advantage over the conventional cascaded
technique.
By cascading the ISL6617 with another ISL6617 or
ISL6611A, it can quadruple the number of phases that
Intersil’s multi-phase controllers ISL63xx can support.
The ISL6617 also features Tri-State input and outputs
that recognize a high-impedance state, working
together with Intersil multiphase PWM controllers and
driver stages to prevent negative transients on the
controlled output voltage when operation is suspended.
This feature eliminates the need for the schottky diode
that may be utilized in a power system to protect the
load from excessive negative output voltage damage.
FN7564
Rev 0.00
February 4, 2010
Features
• Proprietary Phase Doubler scheme with Phase
Shedding Function
(Patent Pending)
• Enhanced Light to Full Load Efficiency
• Double or Quadruple Phase Count
• Patented Current Balancing with DCR Current
Sensing and Adjustable Gain
• Current Monitoring Output (IOUT) to Simplify
System Interface and Layout
• Triple-Level Enable Input for Mode Selection
• Dual PWM Output Drives for Two Synchronous
Rectified Bridges with Single PWM Input
• Channel Synchronization and Two Interleaving
Options
• Tri-State PWM Input and Outputs for Output Stage
Shutdown
• Phase Enable Input and PWM Forced High Output to
Interface with Intersil’s Controller for Phase
Shedding
• Overvoltage Protection
• Dual Flat No-Lead (DFN) Package
- Near Chip-Scale Package Footprint; Improves
PCB Utilization, Thinner Profile
- Pb-Free (RoHS Compliant)
Related Literature
• Technical Brief
TB363
“Guidelines for Handling and
Processing Moisture Sensitive Surface Mount
Devices (SMDs)”
Applications
•
•
•
•
High Current Low Voltage DC/DC Converters
High Frequency and High Efficiency VRM and VRD
High Phase Count and Phase Shedding Applications
5V PWM Input Integrated Power Stage or DrMOS
Pin Configuration
ISL6617
(10 LD DFN)
TOP VIEW
ISENA+
ISENA-
PWMIN
ISENB+
ISENB-
1
2
3
4
5
11
GND
10 PWMA
9 VCC
8 IOUT
7 EN_PH_SYNC
6 PWMB
FN7564 Rev 0.00
February 4, 2010
Page 1 of 15
ISL6617
Functional Pin Descriptions
PIN # PIN SYMBOL
1
2
3
ISENA+
ISENA-
PWMIN
FUNCTION
Output of the differential amplifier for Channel A. Connect a resistor on this pin to the negative rail of
the sensed voltage to set the current gain.
Input of the differential amplifier for Channel A. Typically, the positive rail of sensed voltage via DCR
sensing network connects to this node.
The PWM input signal triggers the J-K flip flop and alternates its input to channel A and B. Both channels
are effectively modulated. The PWM signal can enter three distinct states during operation, see
Operation section for further details. Connect this pin to the PWM output of the controller. The pin is
pulled to VCC when EN_PH_SYNC is low.
Output of the differential amplifier for Channel B. Connect a resistor on this pin to the negative rail of
the sensed voltage to set the current gain.
Input of the differential amplifier for Channel B. Typically, the positive rail of sensed voltage via DCR
sensing network connects to this node.
PWM output of Channel B with Tri-state feature.
4
5
6
7
8
9
10
11
ISENB+
ISENB-
PWMB
EN_PH_SYNC Driver Enable and Mode Selection Input. See Enable and Mode Operation for more details.
IOUT
VCC
PWMA
GND
Current monitoring Output. It sources out the average current of both Channel A and B.
Connect this pin to a +5V bias supply. It supplies power to internal analog circuits. Place a high quality
low ESR ceramic capacitor from this pin to GND.
PWM output of Channel A with Tri-state feature.
Bias and reference ground. All signals are referenced to this node. Place a high quality low ESR ceramic
capacitor from this pin to VCC. Connect this pad to the power ground plane (GND) via thermally
enhanced connection.
Block Diagram
VCC
55k
PWMIN
48k
ISENA-
ISENA+
PWMA
PWMB
ISENB-
ISENB+
CURRENT
BALANCE BLOCK
CHANNEL B
CHANNEL A
CONTROL
LOGIC
EN_PH_SYNC
GND
IOUT
FN7564 Rev 0.00
February 4, 2010
Page 2 of 15
ISL6617
Typical Application (2 Phase Controller for 4 Phase Operation)
+5V
+5V
VCC
PWMA
+5V
FB
COMP
EN_PH_SYNC
ISENA-
VSEN
V
CC
VR_RDY
EN
ISEN1-
ISEN1+
PWM1
PWMIN
ISENA+
ISENB+
ISENB-
ISL6617
IOUT
PWMB
GND
+12V
POWER
STAGE
VIN
PWM PHASE
GND
+V
CORE
+12V
POWER STAGE
VIN
PWM PHASE
GND
VID
MAIN
CONTROL
ISL63XX
FS
+5V
EN_PH_SYNC2
VCC
PWMA
EN_PH_SYNC
ISENA-
ISENA+
ISENB+
ISENB-
ISL6617
+12V
POWER STAGE
VIN
PWM PHASE
GND
PWM2
PWMIN
ISEN2-
ISEN2+
IOUT
PWMB
GND
+12V
POWER
STAGE
VIN
PWM PHASE
GND
GND
FN7564 Rev 0.00
February 4, 2010
Page 3 of 15
ISL6617
Typical Application II (2-Phase Controller to 8-Phase Operation)
+5V
+5V
VCC
PWMA
EN_PH_SYNC
ISENA-
ISENA+
PWMINISENB+
ISENB-
ISL6617
IOUT
PWMB
GND
+12V
POWER STAGE
VIN
PWM PHASE
GND
+5V
+5V
+5V
FB
COMP
VCC
PWMA
VSEN
V
CC
EN_PH_SYNC
ISENA-
ISENA+
+12V POWER
STAGE
VIN
PWM PHASE
GND
+12V
POWER STAGE
VIN
PWM PHASE
GND
+V
CORE
PWM1
PWMIN
+5V
ISL6617
+5V
VCC
PWMA
EN_PH_SYNC
IOUT
ISENA-
ISENA+
ISENB+
PWMIN
ISENB-
VID
ISEN1-
ISEN1+
IOUT
ISENB-
ISENB+
PWMB
FS
GND
ISL6617
PWMB
GND
+12V POWER
STAGE
VIN
PWM PHASE
GND
+12V
POWER STAGE
VIN
MAIN
CONTROL
ISL6336G
+5V
EN_PH_SYNC2
VCC
PWMA
EN_PH_SYNC
ISENA-
ISENA+
+5V
+5V
VCC
PWMA
EN_PH_SYNC
ISENA-
ISENA+
PWMIN ISENB+
ISENB-
ISL6617
IOUT
PWMB
GND
PWM PHASE
GND
+12V POWER
STAGE
VIN
PWM PHASE
GND
+12V
POWER STAGE
VIN
PWM2
PWMIN
+5V
ISL6617
+5V
VCC
PWMA
EN_PH_SYNC
IOUT
PWM PHASE
GND
ISEN2-
ISEN2+
IOUT
ISENB-
ISENB+
ISENA-
ISENA+
ISENB+
ISENB-
GND
PWMB
GND
PWMIN
ISL6617
PWMB
GND
+12V POWER
STAGE
VIN
PWM PHASE
GND
FN7564 Rev 0.00
February 4, 2010
Page 4 of 15
ISL6617
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
ISL6617CRZ
ISL6617IRZ
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to
TB347
for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for
ISL6617.
For more information on MSL, please
see Technical Brief
TB363.
617C
617I
PART
MARKING
TEMP. RANGE
(°C)
0 to +70
-40 to +85
PACKAGE
(Pb-Free)
10 Ld 3x3 DFN
10 Ld 3x3 DFN
PKG.
DWG. #
L10.3x3
L10.3x3
FN7564 Rev 0.00
February 4, 2010
Page 5 of 15
电机驱动控制（Motor Control）
