Power Factor Correction Controllers
ISL6730A, ISL6730B, ISL6730C, ISL6730D
The ISL6730A, ISL6730B, ISL6730C, ISL6730D are active
Features
Power Factor Correction (PFC) controller ICs that use a boost
topology. The controllers are suitable for AC/DC power
systems, up to 2kW and over the universal line input.
The ISL6730A, ISL6730B, ISL6730C, ISL6730D operate in
Continuous Conduction Mode (CCM). Accurate input current
shaping is achieved with a current error amplifier. A patent
pending breakthrough negative capacitance technology
minimizes zero crossing distortion and reduces the magnetic
components size. The small external components result in a
low cost design without sacrificing performance.
The internally clamped 12.5V gate driver delivers 1.5A peak
current to the external power MOSFET. The ISL6730A,
ISL6730B, ISL6730C, ISL6730D provide a highly reliable
system that is fully protected. Protection features include
cycle-by-cycle overcurrent, over power limit, over-temperature,
input brownout, output overvoltage and undervoltage
protection.
The ISL6730A, ISL6730B provide excellent power efficiency
and transitions into a power saving skip mode during light load
conditions, thus improving efficiency automatically. The
ISL6730A, ISL6730B, ISL6730C, ISL6730D can be shut down
by pulling the FB pin below 0.5V or grounding the BO pin. The
ISL6730C, ISL6730D have no skip mode.
Two switching frequency options are provided. The ISL6730B,
ISL6730D switch at 62kHz, and the ISL6730A, ISL6730C
switch at 124kHz.
• Reduce component size requirements
- Enables smaller, thinner AC/DC adapters
- Choke and cap size can be reduced
- Lower cost of materials
• Excellent power factor over line and load regulation
- Internal current compensation
- CCM Mode with Patent pending IP for smaller EMI filter
• Better light load efficiency
- Automatic pulse skipping
- Programmable or automatic shutdown
• High reliable design
- Cycle-by-cycle current limit
- Input average power limit
- OVP and OTP protection
- Input brownout protection
• Small 10 Ld MSOP package
Applications
• Desktop computer AC/DC adaptor
• Laptop computer AC/DC adaptor
• TV AC/DC power supply
• AC/DC brick converters
V
I
V
LINE
+
100
V
OUT
95
90
EFFICIENCY (%)
85
80
75
70
65
60
0
20
40
60
OUTPUT POWER (W)
80
100
ISL6730C
ISL6730A, SKIP
VCC
ISEN
ICOMP
VIN
GATE
GND
ISL6730
FB
COMP
BO
VREG
FIGURE 1. TYPICAL APPLICATION
FIGURE 2. PFC EFFICIENCY
TABLE 1. KEY DIFFERENCES IN FAMILY OF ISL6730
VERSION
Switching Frequency
Skip Mode
ISL6730A
124kHz
Yes-Fixed
ISL6730B
62kHz
Yes-Fixed
ISL6730C
124kHz
No
ISL6730D
62kHz
No
August 8, 2013
FN8258.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Copyright Intersil Americas LLC 2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL6730A, ISL6730B, ISL6730C, ISL6730D
Pin Configuration
ISL6730A, ISL6730B, ISL6730C, ISL6730D
(10 LD MSOP)
TOP VIEW
GND
ISEN
ICOMP
VIN
BO
1
2
3
4
5
10 GATE
9 VCC
8 VREG
7 FB
6 COMP
Pin Descriptions
PIN # I/O SYMBOL
1
2
3
4
-
I
I/O
I
GND
ISEN
ICOMP
VIN
Ground pin. All voltage levels refer to this pin.
Current sense pin. The current through this pin is proportional to the inductor current.
Current error amplifier output pin.
Input voltage sense. This pin provides the reference voltage to shape inductor current. Connect this pin to a resistor divider from
the rectified input voltage. The resistor divider ratio is used to adjust the phase lag between input voltage and the input current.
The phase lag is required to compensate the phase lead generated by the EMI filter.
This pin should be decoupled to GND with a minimum 0.1µF ceramic capacitor. The BO pin is a voltage follower, which will follow
the DC voltage of the VIN pin. The BO pin is internally tied to GND through a resistor R
IS
. The decoupling capacitor provides ripple
filtering. When the voltage at the BO pin (V
BO
) drops below brownout voltage threshold, the controller enters shutdown mode
and the gate drive is disabled. The BO pin will be disabled when the FB pin drops below the enabling threshold.
Output of the error amplifier. The voltage of the COMP pin sets the input power. During start-up, a small charge current will slowly
ramp up the voltage of the COMP pin.
Voltage feed back pin. Connect this pin to a resistor divider from the output. The resistor divider sets the output voltage. When
the FB pin voltage exceeds 104% of the reference voltage, overvoltage-protection is triggered and gate drive is disabled. When
the FB pin is below 10%, the device is put into shutdown mode. There is an internal pull-down current source for open loop
protection.
Output of internal regulator. The voltage having a ±2% tolerance over line, load and operating temperature. Bypass to GND with
a 47nF low ESR capacitor. VREG can source up to 10mA. This pin is not recommended for usage other than bypass.
Power supply pin. The VCC pin should be decoupled to GND with a minimum 0.1µF ceramic capacitor.
Push-pull gate drive for the external MOSFET. Output voltage is clamped at 12.5V. This pin provides typically 2A sink and 1.5A
source capability.
DESCRIPTION
5
I/O
BO
6
7
I/O
I
COMP
FB
8
9
10
-
I
O
VREG
VCC
GATE
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
ISL6730AFUZ
ISL6730BFUZ
ISL6730CFUZ
ISL6730DFUZ
ISL6730AEVAL1Z
ISL6730BEVAL1Z
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to
TB347
for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page. For more information on MSL please see techbrief
TB363.
6730A
6730B
6730C
6730D
Evaluation Board
Evaluation Board
PART
MARKING
TEMP.
RANGE (°C)
-40 to +125
-40 to +125
-40 to +125
-40 to +125
PACKAGE
(Pb-Free)
10 Ld MSOP
10 Ld MSOP
10 Ld MSOP
10 Ld MSOP
M10.118
M10.118
M10.118
M10.118
PKG.
DWG. #
2
FN8258.1
August 8, 2013
Block Diagram
EMI CHOKE
V
I
L
D
V
OUT
Q
1
C
OUT
V
LINE
C
F3
C
F2
L
m
C
F1
D
F1
D
F2
ISL6730A, ISL6730B, ISL6730C, ISL6730D
R
CS
C
REG
VCC
VREG
3
R
IN2
R
IN1
FN8258.1
August 8, 2013
CURRENT
MIRROR
UVLO
LINEAR
REGULATOR
VCC
GATE
2:1
R
SEN
ISEN
I
CS
I
I
OC
> -------------
-
2
OTP
PWM
COMP
CEQ GEN.
ICOMP
IREF
Gmi
0.25
×
VIN
-----------------------------COMPB
2
BO
VIN
COMPB
V
R
×
I
IS
ISEN
= ----------------------------------
-
CS
2
OSCILLATOR
SOFT-START
ENABLE
2.5V
SKIP
CONTROL
LOGIC
CS
GND
R
IS
SKIP
CLAMP
COMP-1V
FB
OVER POWER
LIMIT
Gmv
R
FB2
20µA
I
FB
SKIP
BO
C
BO
COMP
R
FB1
Application Schematics
Typical 300W Application Schematic
D1
1N5406
L1
0u
AC1
2
3
F2 8A
UNIVERSAL INPUT
85~265Vac
100n
C2
1
4
R1
2M
5mH
L3
R3
2M
+
P1
L2
1.5mH
D2
2
VOUT
1
DC+
TP9
P2
C3D04060
SPP20N60C3
Q1
TP12
GATE1
1
R2
2.2
ISL6730A, ISL6730B, ISL6730C, ISL6730D
DB1
GBU808
C22
680n
-
C3
470n
C4
DNP
2
1
C1
390V
270u
450V
C21
0.1
C19
0.1
2
P3
TP10
3.3M
R6
C26
DNP
GND
R10
VCC
GND
R26
49.9
P4
AC2
C5
2.2n
C6
2.2n
D7
S1M
D8
S1M
C11
R8
470k
R11
470k
VIN
C7
1u
R9
3k
ISEN
TP5
TP3
C12
DNP
R13
7.15k
C13
220p
VCC
R21
25k
DNP
1
DNP
R20
10k
DNP
P9
330p
ICOMP
TP6
3
2
4
R28 0.22
R27 0.22
R5 0.22
C8
220n
47n
C20
VREG
TP8
U1
8
C9
1u
9
VCC
R4
51k
P5
DNP
PE
DZ1
3.3V
R14
8.2k
C10
1nF
3
R EG
VC C
C OM P
BO
5
6
3
2
4
FN8258.1
August 8, 2013
GATE
GND
10
1
3.3M
TP7
GATE
DNP
P6
ICOMP
ISEN
VIN
P7
FB
7
TP1
R17
0
FB
ISL6730B/D
TP2
COMP
C16
1n
TP4
2N7002
Q2
DNP
BO
R18
62k
C14
470n
C18
2.2u
R19
42.2k
DNP
P8
C15
150n
C17
1n
DNP
Application Schematics
(Continued)
Typical 85W Application Schematic
S3KB-TP
S3KB-TP
F1 3.15A
P1
AC1
2
3
R1
2M
7.5mH
L3
R3
2M
C6
470p
D7
S1M
D8
S1M
1
4
C3
330n
C4
DNP
D3
D4
L1 0uH
L2 2.2m
S3KB-TP
D1
2
VOUT
1
D2
DC+
TP9
3
C3D04060E
ISL6730A, ISL6730B, ISL6730C, ISL6730D
P2
IPP60R600C6
Q1
1
R2
2.2
D5
D6
S3KB-TP
S3KB-TP
0.22
R5
C8
220n
R9
2.1k
R14
5.36k
8
C10
6.8n
3
2
4
C13
220p
VCC
R21
25k
DNP
1
DNP
R20
10k
DNP
P9
C9
1u
C24
47n
U1
VCC
VCC
GATE
GND
ISEN
VIN
BO
10
1
TP7
GATE
R10
3.3M
COMP
FB
7
TP1
R17
1.5k
R19
40.2k
FB
GND
P7
9
R4
51k
3
2
1
390V
2
REG
ICOMP
R11
470k
VIN
TP3
C12
DNP
R13
7.15k
ISEN
TP5
TP6
ICOMP
VCC
5
6
3
2
5
UNIVERSAL INPUT
85~265Vac
100n
C2
P4
AC2
P5
DNP
PE
C1
56u
450V
P3
TP10
C5
470p
DZ1
3.3V
3.3M
R6
C26
DNP
DNP
GND
C11
470p
R8
470k
P6
ISL6730A/C
TP2
COMP
C16
1n
TP4
2N7002
Q2
DNP
VIN
R18
68k
C14
470n
C18
2.2u
DNP
P8
C15
100n
C17
1n
DNP
FN8258.1
August 8, 2013
嵌入式系统
