DATASHEET
ISL78225
4-Phase Interleaved Boost PWM Controller with Light Load Efficiency
Enhancement
The ISL78225 4-phase controller is targeted for applications
where high efficiency (>95%) and high power are required. The
multiphase boost converter architecture uses interleaved
timing to multiply channel ripple frequency and reduce input
and output ripple. Lower ripple results in fewer input/output
capacitors and therefore lower component cost and smaller
implementation area.
The ISL78225 has a dedicated pin to initiate the phase
dropping scheme for higher efficiency at light load by dropping
phases based on the load current, so the switching and core
losses in the converter are reduced significantly. As the load
increases, the dropped phase(s) are added back to
accommodate heavy load transients and improve efficiency.
Input current is sensed continuously by measuring the voltage
across a dedicated current sense resistor or inductor DCR. This
current sensing provides precision channel-current balancing,
and per-phase overcurrent protection. A separate totalizing
current limit function provides overcurrent protection for all the
phases combined. This two-stage current protection provides
maximum performance and circuit reliability.
The ISL78225 can also provide for input voltage tracking via the
VREF2 pin. The comparison reference voltage will be the lower
of the VREF2 pin or the internal 2V reference. By using a resistor
network between VIN and VREF2 pin, the output voltage can
track input voltage to limit the output power during automotive
cranking conditions.
The ISL78225 can output a clock signal for expanding operation
to 8 phases, which offers high system flexibility. The
threshold-sensitive enable input is available to accurately
coordinate the start-up of the ISL78225 with any other voltage
rail.
FN7909
Rev 4.00
September 5, 2014
Features
• Peak current mode PWM control with adjustable slope
compensation
• Precision resistor/DCR current sensing
• 2-, 3- or 4-phase operation
• Adjustable phase dropping/diode emulation/pulse skipping
for high efficiency at light load
• Phase dropping facilitated with companion FET driver
ISL78420 (featuring tri-level input control)
• Adjustable switching frequency or external synchronization
from 75kHz up to 1MHz per phase
• Over-temperature/overvoltage protection
• 2V
1.0%
internal reference
• Pb-free 44 Ld 10x10 EP-TQFP (RoHS compliant)
• -40°C to +125°C operating temperature range
• AEC-Q100 qualified
Applications
• Automotive power supplies
- Start/stop DC/DC converter
- Electronic power steering systems (EPAS)
- Fuel pumps
- Injection system
• Audio trunk amplifier power supplies
• Telecom and industrial power supplies
0.98
WITH PHASE DROPPING
WITHOUT PHASE DROPPING
0.93
EFFICIENCY (%)
0.88
0.83
0.78
16V INPUT, 36V OUTPUT
SYNCHRONOUS BOOST
0
1
2
3
4
5
6
7
8
9
10
OUTPUT CURRENT (A)
0.73
FIGURE 1. EFFICIENCY vs OUTPUT CURRENT vs PHASE DROPPING MODE
FN7909 Rev 4.00
September 5, 2014
Page 1 of 22
ISL78225
Pin Configuration
ISL78225
(44 LD 10x10 EP-TQFP)
TOP VIEW
VOUT_OVB
VOUT_SEN
VIN_OVB
VIN_SEN
PGOOD
MODE
DMAX
IOUT
GND
FS
SS
COMP
FB
VREF2
GND
SLOPE
PLL_COMP
SYNC
CLK_OUT
PWM_INV
1
44 43 42 41 40 39 38 37 36 35 34
33
2
32
3
4
5
6
7
8
9
31
30
29
28
27
26
25
24
VCC
EN
VIN
DNC
DNC
ISEN4P
ISEN4N
ISEN2P
ISEN2N
DNC
DNC
ISEN3P
ISEN3N
10
11
23
12 13 14 15 16 17 18 19 20 21 22
DRIVE_EN
DNC
ISEN1N
P_COM
PWM_TRI
Functional Pin Descriptions
PIN #
1
2
3
4
5
SYMBOL
FS
SS
COMP
FB
VREF2
DESCRIPTION
A resistor placed from FS to ground will set the PWM switching frequency.
Use this pin to set up the desired soft-start time. A capacitor placed from SS to ground will set up the soft-start
ramp rate and in turn determine the soft-start time.
The output of the transconductance amplifier. Place the compensation network between COMP and GND for
compensation loop design.
The inverting input of the transconductance amplifier. A resistor network should be placed between the FB pin and
output rail to set the output voltage.
External reference input to the transconductance amplifier. When the VREF2 pin voltage drops below 1.8V, the
internal reference will be shifted from 2V to VREF2. The VREF2 voltage can be programmed by connecting a
resistor divider network from VCC or VIN.
Bias and reference ground for the IC.
This pin programs the slope of the internal slope compensation. A resistor should be connected from the SLOPE
pin to GND. Please refer to
“Adjustable Slope Compensation” on page 18
for how to choose the resistor value.
This pin serves as the compensation node for the PLL. A second order passive loop filter connected between
PLL_COMP pin and GND compensates the PLL feedback loop.
Frequency synchronization pin. Connecting the SYNC pin to an external square pulse waveform (typically 20% to
80% duty cycle) will synchronize the converter switching frequency to the fundamental frequency of the input
waveform. If SYNC function is not used, tie the SYNC pin to GND. A 500nA current source is connected internally
to pull-down the SYNC pin if it is left open.
This pin provides a clock signal to synchronize with another ISL78225. This provides scalability and flexibility. The
rising edge signal on the CLKOUT pin is in phase with the leading edge of the PWM1 signal.
This pin determines the polarity of the PWM output signal. Pulling this pin to GND will force normal operation with
inverting MOSFET drivers. Pulling this pin to VCC will invert the PWM signal for operation with non-inverting
MOSFET drivers. This function provides the flexibility for the ISL78225 to work with different drivers.
6
7
8
9
GND
SLOPE
PLL_COMP
SYNC
10
11
CLK_OUT
PWM_INV
FN7909 Rev 4.00
September 5, 2014
ISEN1P
PWM4
PWM1
PWM3
PWM2
DNC
Page 2 of 22
ISL78225
Functional Pin Descriptions
PIN #
12
SYMBOL
PWM_TRI
(Continued)
DESCRIPTION
This pin enables the tri-level of the PWM output signal. Pulling this pin to GND forces the PWM output to be
traditional two level logic. Pulling the PWM_TRI pin to VCC will enable tri-level PWM signals, then the PWM output
can be at the 2.5V tri-level condition.
Pulse width modulation outputs. Connect these pins to the PWM input pins of the external driver ICs. The number
of active channels is determined by the state of PWM3, PWM4. For 2-phase operation, connect PWM3 to VCC;
similarly, connect PWM4 to VCC for 3-phase operation.
PWM Compensation pin; connect this pin through resistor to VCC.
Driver enable output pin. This pin is connected to the enable pin of MOSFET drivers.
Do Not Connect – These pins must be left floating.
13, 14, 16,
17
15
19
18, 20,
25, 26, 31,
32
PWM1, PWM3, PWM2,
PWM4
P_COM
DRIVE_EN
DNC
21, 22, 23, ISEN1N, ISEN1P, ISEN3N, The ISENxP and ISENxN pins are current sense inputs to individual differential amplifiers. The sensed current is
24, 27, 28, ISEN3P, ISEN2N, ISEN2P, used as a reference for current mode control and overcurrent protection. Inactive channels should have their
respective ISENxN pins connected to VIN and ISENxP pins left open or tied to VIN. The ISL78225 utilizes external
ISEN4N, ISEN4P
29, 30
sense resistor current sensing method or Inductor DCR sensing method.
33
34
VIN
VCC
Connect input rail to this pin. This pin is connected to the internal linear regulator, generating the power necessary
to operate the chip. It is recommended the DC voltage applied to the VIN pin does not exceed 40V.
This pin is the output of the internal linear regulator that supplies the bias and gate voltage for the IC. A minimum
4.7µF decoupling ceramic capacitor should be connected from VCC to GND. The controller starts to operate when
the voltage on this pin exceeds the rising POR threshold and shuts down when the voltage on this pin drops below
the falling POR threshold. This pin can be connected directly to a +5V supply if VIN falls below 5.6V.
Bias and reference ground for the IC.
Mode selection pin. Pull this pin to logic HIGH for forced PWM mode; phase dropping/adding is inactive during
forced PWM mode. Connecting a resistor from MODE pin to GND will initialize phase dropping mode (PDM). In
PDM, a 5µA fixed reference current will flow out of the MODE pin, and the phase dropping threshold can be
programmed by adjusting the resistor value.
IOUT is the current monitor pin with an additional OCP adjustment function. An RC network needs to be placed
between IOUT and GND to ensure the proper operation. The voltage at the IOUT pin will be proportional to the input
current. If the voltage on the IOUT pin is higher than 2V, ISL78225 will go into overcurrent protection mode and
the chip will latch off until the EN pin is toggled.
The VIN_SEN pin is used for sensing the VIN voltage. A resistor divider network is connected between this pin and
boost power stage input voltage rail. When the voltage on VIN_SEN is greater than 2.4V, the VIN_OVB pin will be
pulled low to indicate an input overvoltage condition. The threshold voltage can be programmed by changing the
divider ratios.
The VIN_OVB pin is an open-drain indicator of an overvoltage condition at the input. When the voltage on the
VIN_SEN pin is greater than the 2.4V threshold, the VIN_OVB pin will be pulled low.
The VOUT_SEN pin is used for sensing the output voltage; a resistor divider network is connected between this pin
and output voltage rail. When the voltage on VOUT_SEN pin is greater than 2.4V, VOUT_OVB pin will be pulled low,
indicating an output overvoltage condition.
The VOUT_OVB pin is an open-drain indicator of an overvoltage condition at the output. When the voltage on the
VOUT_SEN pin is greater than the 2.4V threshold, the VOUT_OVB pin will be pulled low and latched, toggling VIN
or EN will reset the latch.
DMAX pin sets the maximum duty cycle of the PWM modulator. If the DMAX pin is connected to GND, the
maximum duty cycle will be set to 91.7%. Floating this pin will limit the duty cycle to 75% and connecting the
DMAX pin to VCC will limit the duty cycle to 83.3%.
This pin is a threshold-sensitive enable input for the controller. Connecting the power supply input to EN pin
through an appropriate resistor divider provides a means to synchronize power-up of the controller and the
MOSFET driver ICs. When EN pin is driven above 1.2V, the ISL78225 is active depending on status of the internal
POR, and pending fault states. Driving the EN pin below 1.1V will clear all fault states and the ISL78225 will
soft-start when re-enabled.
This pin is used as an indication of the end of soft-start and output regulation. It is an open-drain logic output that
is low impedance until the soft-start is completed. It will be pulled low again once the UV/OV/OC/OT conditions
are detected.
It is recommended to solder the Exposed Pad to the ground plane.
35
36
GND
MODE
37
IOUT
38
VIN_SEN
39
40
VIN_OVB
VOUT_SEN
41
VOUT_OVB
42
DMAX
43
EN
44
PGOOD
Exposed Pad
FN7909 Rev 4.00
September 5, 2014
Page 3 of 22
ISL78225
Ordering Information
PART NUMBER
(Notes
1, 2, 3)
ISL78225ANEZ
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to
TB347
for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for
ISL78225.
For more information on MSL please see techbrief
TB363.
PART
MARKING
ISL78225 ANEZ
TEMP RANGE
(°C)
-40 to +125
PACKAGE
(Pb-free)
44 Ld EP-TQFP
PKG.
DWG. #
Q44.10x10A
ISL78225 Block Diagram
VIN_OVB
VOUT_SEN
PGOOD
VOUT_OVB
SYNC
PLL_COMP
VIN_SEN
2.4V
VIN
VCC
5V LDO
OV_IN
REF
2V
2.4V
OC_ALL
OC_PH
OV_OUT
OV_IN
UV
OC
OT
FAULT CONTROL
CIRCUITS
SYNC
DETECT
S
POR
Q
R
2.4V
FB
OV_OUT
DMAX
VCO
CLK_OUT
DMAX
FS
UV
SLOPE
COMPENSATION
SLOPE
EN
1.2V
OVER
TEMP
5µA
SS
SOFT- START LOGIC
DRIVE_EN
OT
0.8Vref
20k
DUPLICATE FOR EACH CHANNEL
S
2V
R1
Gm
DMAX
OT
OC
OV_OUT
PH3
PH4
R2
Q
OC_PH
ISEN1
IOUT1
160µA
ZCD
ISEN1P
CSA
ISEN1N
(FOR PH1 &
PH2 ONLY)
VREF2
FB
PWM CONTROL
PWM1
COMP
PWM_TRI
PWM_INV
MODE
MODE
PHASE DROP CONTROL
IOUT1
ADDER
IOUT
2V
IOUT4
OC_ALL
GND
P_COM
FN7909 Rev 4.00
September 5, 2014
Page 4 of 22
Typical Application 1: 4-Phase Synchronous Boost Converter with Sense Resistor Current
Sensing
VOUT_SEN
VOUT_SEN
VIN_OVB
VIN_SEN
EN
PGOOD
DMAX
IOUT
FS
VOUT_OVB
MODE
GND
VCC
DRIVE_EN
P_COM
ISEN1N
PWM1
PWM3
PWM2
PWM4
NC
NC
PWM1
PWM3
PWM2
VCC
ISEN1P
ISEN1N
Note: Please see ISL78420 for an Automotive Qualified 100V synchronous boost driver.
PWM4
FN7909 Rev 4.00
September 5, 2014
Page 5 of 22
ISL78225
VIN
+
VCC
EN
UGATE
PHASE
DRIVER
PWM1
PWM
LGATE
Phase 1
VOUT_SEN
VIN
NC
NC
ISEN4P
ISEN4N
ISEN2P
ISEN2N
SS
COMP
FB
VCC
VREF2
GND
SLOPE
PLL_COMP
SYNC
CLK_OUT
PWM_INV
PWM_TRI
EN
ISEN2P
ISEN2N
PWM2
EN
ISEN3P
ISEN3N
PWM3
EN
ISEN4P
ISEN4N
PWM4
Phase 2
VOUT
ISEN4P
ISEN4N
ISL78225
ISEN2P
ISEN2N
NC
NC
ISEN3P
ISEN3N
ISEN1P
Phase 3
LOAD
Phase 4
ISEN3P
ISEN3N
+
