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ISL80103IR18Z-T13

ADJUSTABLE POSITIVE LDO REGULATOR

器件类别:电源/电源管理    电源电路   

厂商名称:Intersil ( Renesas )

厂商官网:http://www.intersil.com/cda/home/

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器件参数
参数名称
属性值
Objectid
1324287078
包装说明
,
Reach Compliance Code
unknown
ECCN代码
EAR99
调节器类型
ADJUSTABLE POSITIVE SINGLE OUTPUT LDO REGULATOR
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High Performance 2A and 3A Linear Regulators
ISL80102, ISL80103
The ISL80102 and ISL80103 are low voltage, high-current, single
output LDOs specified for 2A and 3A output current, respectively.
These LDOs operate from the input voltages of 2.2V to 6V and
are capable of providing the output voltages of 0.8V to 5V on the
adjustable V
OUT
versions. Fixed output voltage options are
available in 1.8V, 2.5V, 3.3V and 5V. Other custom voltage
options available upon request.
For applications that demand in-rush current less than the
current limit, an external capacitor on the soft-start pin provides
adjustment. The ENABLE feature allows the part to be placed into
a low quiescent current shutdown mode. A sub-micron BiCMOS
process is utilized for this product family to deliver the best in
class analog performance and overall value.
These CMOS (LDOs) will consume significantly lower quiescent
current as a function of load over bipolar LDOs, which translates
into higher efficiency and the ability to consider packages with
smaller footprints. The quiescent current has been modestly
compromised to enable a leading class fast load transient
response, and hence a lower total AC regulation band for an LDO
in this category.
Features
• Stable with all capacitor types (Note 10)
• 2A and 3A output current ratings
• 2.2V to 6V input voltage range
• ±1.8% V
OUT
accuracy guaranteed over line, load and
T
J
= -40°C to +125°C
• Very low 120mV dropout voltage at 3A (ISL80103)
• Fixed and adjustable V
OUT
versions
• Very fast transient response
• Excellent 62dB PSRR
• 100µV
RMS
output noise
• Power-good output
• Adjustable in-rush current limiting
• Short circuit and over-temperature protection
• Available in a 10 Ld DFN
• Servers
• Telecommunications and networking
• Medical equipment
• Instrumentation systems
• Routers and switchers
ISL80102, ISL80103
2.5V ±10%
V
IN
C
IN
10µF
1.8V ±1.8%
9
10
1
V
IN
V
IN
V
OUT
V
OUT
2
C
OUT
10µF
V
OUT
R
PG
ON
OFF
7
6
*C
SS
ENABLE
SS
GND
5
*CSS is optional, (see Note 11) on page 5.
SENSE
3
100kΩ
4
PG
PGOOD
FIGURE 1. TYPICAL APPLICATION
June 14, 2013
FN6660.6
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Copyright Intersil Americas LLC 2009-2012, 2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL80102, ISL80103
Block Diagram
VIN
R5
10µA
10µA
M5
M4
M3
M1
POWER PMOS
IL/10,000
IL
VOUT
R8
R7
R9
+
-
EN
EN
+
-
M6
-
+
EN
500mV
LEVEL
SHIFT
R1
R2
SENSE
R4
ADJ
PG
M2
*R3
GND
EN
ENABLE
SS
M8
EN
M7
V TO I
500mV
+
-
485mV
+
-
-
+
*R3 is open for ADJ versions.
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
ISL80102IRAJZ
ISL80102IR18Z
ISL80102IR25Z
ISL80103IRAJZ
ISL80103IR18Z
ISL80103IR25Z
ISL80102EVAL2Z
ISL80103EVAL2Z
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to
TB347
for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for
ISL80102, ISL80103.
For more information on MSL please see tech brief
TB363.
DZJA
DZNA
DZPA
DZAA
DZEA
DZFA
Evaluation Board
Evaluation Board
PART
MARKING
V
OUT
VOLTAGE
ADJ
1.8V
2.5V
ADJ
1.8V
2.5V
TEMP. RANGE
(°C)
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
PACKAGE
(Pb-Free)
10 Ld 3x3 DFN
10 Ld 3x3 DFN
10 Ld 3x3 DFN
10 Ld 3x3 DFN
10 Ld 3x3 DFN
10 Ld 3x3 DFN
PKG
DWG. #
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
2
FN6660.6
June 14, 2013
ISL80102, ISL80103
Pin Configuration
ISL80102, ISL80103
(10 LD 3x3 DFN)
TOP VIEW
V
OUT
V
OUT
SENSE/ADJ
PG
GND
1
2
3
4
5
10 V
IN
9 V
IN
8 DNC
7 ENABLE
6 SS
Pin Descriptions
PIN NUMBER
1, 2
3
4
5
6
7
8
9, 10
PIN NAME
VOUT
SENSE/ADJ
PG
GND
SS
ENABLE
DNC
VIN
EPAD
Output voltage pin.
Remote voltage sense for internally fixed VOUT options. ADJ pin for externally set VOUT.
VOUT in regulation signal. Logic low defines when VOUT is not in regulation. Must be grounded if not used.
GND pin.
External cap adjusts in-rush current.
VIN independent chip enable. TTL and CMOS compatible.
Do not connect this pin to ground or supply. Leave floating.
Input supply pin.
EPAD must be connected to copper plane with as many vias as possible for proper electrical and optimal thermal
performance.
DESCRIPTION
Typical Application
ISL80102, ISL80103
2.5V ±10%
V
IN
C
IN
10µF
R
1
10kΩ
7
6
*C
SS
PG
ENABLE
**C
PB
SS
GND
5
ADJ
3
1500pF
R
3
2.61kΩ
4
PGOOD
9
10
V
IN
V
IN
V
OUT
V
OUT
1
2
C
OUT
10µF
R
PG
100kΩ
1.8V
V
OUT
EN
OPEN DRAIN COMPATIBLE
R
4
1.0kΩ
*CSS is optional, (see Note 11) on page 5.
**C
PB
is optional. See “Functional Description” on page 12 for more information.
FIGURE 2. TYPICAL APPLICATION DIAGRAM
3
FN6660.6
June 14, 2013
ISL80102, ISL80103
Absolute Maximum Ratings
(Note 6)
V
IN
Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
V
OUT
Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
PG, ENABLE, SENSE/ADJ, SS, Relative to GND. . . . . . . . . . . -0.3V to +6.5V
Thermal Information
Thermal Resistance (Typical)
θ
JA
(°C/W)
θ
JC
(°C/W)
10 Ld 3x3 DFN Package (Notes 4, 5). . . . .
45
4
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
(Note 8)
Junction Temperature Range (T
J
) . . . . . . . . . . . . . . . . . . .-40°C to +125°C
VIN Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.2V to 6V
V
OUT
Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800mV to 5V
PG, ENABLE, SENSE/ADJ, SS Relative to GND . . . . . . . . . . . . . . . . 0V to 6V
PG Sink Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4.
θ
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief
TB379.
5. For
θ
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
6. ABS max voltage rating is defined as the voltage applied for a lifetime average duty cycle above 6V of 1%.
7. Electromigration specification defined as lifetime average junction temperature of +110°C where max rated DC current = lifetime average current.
Electrical Specifications
Unless otherwise noted, all parameters are established over the following specified conditions:
V
IN
= V
OUT
+ 0.4V, V
OUT
= 1.8V, C
IN
= C
OUT
= 10
µ
F, T
J
= +25
°
C,
I
LOAD
= 0A.
Applications must follow thermal guidelines of the package to
determine worst case junction temperature. Please refer to “Functional Description” on page 12 and Tech Brief
TB379
.
Boldface limits apply over the operating temperature range, -40°C to +125°C. Pulse load techniques used by ATE to ensure T
J
= T
A
defines
established limits.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 8)
TYP
MAX
(Note 8)
UNITS
DC CHARACTERISTICS
DC Output Voltage Accuracy
V
OUT
V
OUT
Options: 1.8V.
V
IN
=2.2V; I
LOAD
= 0A
V
OUT
Options: 1.8V.
2.2V < V
IN
< 3.6V; 0A < I
LOAD
< 3A
V
OUT
Options: 2.5V
V
IN
=V
OUT
+ 0.4V; I
LOAD
= 0A
V
OUT
Options: 2.5V
V
OUT
+ 0.4V < V
IN
< 6V; 0A < I
LOAD
< 3A
Feedback Pin (ADJ Version)
DC Input Line Regulation
V
FB
ΔV
OUT
/ΔV
IN
ΔV
OUT
/ΔI
OUT
2.2V < V
IN
< 6V, 0A < I
LOAD
< 3A
V
OUT
+ 0.4V < V
IN
< 3.6V, V
OUT
= 1.8V
V
OUT
+ 0.4V < V
IN
< 6V, V
OUT
= 2.5V
DC Output Load Regulation
0A < I
LOAD
< 3A, All voltage options
0A < I
LOAD
< 2A, All voltage options
Feedback Input Current
Ground Pin Current
I
Q
I
SHDN
V
DO
ISC
V
ADJ
= 0.5V
I
LOAD
= 0A, 2.2V < V
IN
< 6V
I
LOAD
= 3A, 2.2V < V
IN
< 6V
Ground Pin Current in Shutdown
ENABLE Pin = 0.2V, V
IN
= 5V
ENABLE Pin = 0.2V, V
IN
= 6V
Dropout Voltage (Note 9)
I
LOAD
= 3A, V
OUT
= 2.5V, 10 LD 3x3 DFN
I
LOAD
= 2A, V
OUT
= 2.5V, 10 LD 3x3 DFN
Output Short Circuit Current
(3A Version)
Output Short Circuit Current
(2A Version)
V
OUT
= 0V, V
OUT
+ 0.4V < V
IN
< 6V
V
OUT
= 0V, V
OUT
+ 0.4V < V
IN
< 6V
-0.8
-0.6
0.01
7.5
8.5
0.4
3.3
120
81
5.0
2.8
16
185
125
1
9
12
-1.8
491
500
0.1
0.1
-1.8
0.5
-1.8
509
0.4
0.8
0.5
1.8
%
%
%
%
mV
%
%
%
%
µA
mA
mA
µA
µA
mV
mV
A
A
4
FN6660.6
June 14, 2013
ISL80102, ISL80103
Unless otherwise noted, all parameters are established over the following specified conditions:
V
IN
= V
OUT
+ 0.4V, V
OUT
= 1.8V, C
IN
= C
OUT
= 10
µ
F, T
J
= +25
°
C,
I
LOAD
= 0A.
Applications must follow thermal guidelines of the package to
determine worst case junction temperature. Please refer to “Functional Description” on page 12 and Tech Brief
TB379
.
Boldface limits apply over the operating temperature range, -40°C to +125°C. Pulse load techniques used by ATE to ensure T
J
= T
A
defines
established limits. (Continued)
PARAMETER
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
(Rising Threshold)
SYMBOL
TSD
TSDn
TEST CONDITIONS
V
OUT
+ 0.4V < V
IN
< 6V
V
OUT
+ 0.4V < V
IN
< 6V
MIN
(Note 8)
TYP
160
15
MAX
(Note 8)
UNITS
°C
Electrical Specifications
°
C
AC CHARACTERISTICS
Input Supply Ripple Rejection
PSRR
f = 1kHz, I
LOAD
= 1A; V
IN
= 2.2V
f = 120Hz, I
LOAD
= 1A; V
IN
= 2.2V
Output Noise Voltage
I
LOAD
= 10mA, BW = 300Hz < f < 300kHz
V
EN(HIGH)
V
EN(LOW)
V
EN(HYS)
t
EN
2.2V < V
IN
< 6V
2.2V < V
IN
< 6V
2.2V < V
IN
< 6V
C
OUT
= 10µF, I
LOAD
= 1A
V
IN
= 6V, EN = 3V
R
PD
I
CHG
-7
323
-4.5
-2
0.616
0.463
55
62
100
dB
dB
µV
RMS
0.95
V
V
mV
µs
1
µA
ENABLE PIN CHARACTERISTICS
Turn-on Threshold
Turn-off Threshold
Hysteresis
Enable Pin Turn-on Delay
Enable Pin Leakage Current
0.8
0.6
135
150
SOFT-START CHARACTERISTICS
Reset Pull-Down resistance
Soft-Start Charge Current
Ω
µA
PG PIN CHARACTERISTICS
V
OUT
PG Flag Threshold
V
OUT
PG Flag Hysteresis
PG Flag Low Voltage
PG Flag Leakage Current
NOTES:
8. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
9. Dropout is defined by the difference in supply V
IN
and V
OUT
when the supply produces a 2% drop in V
OUT
from its nominal value.
10. Minimum cap of 10µF X5R/X7R on V
IN
and V
OUT
required for stability.
11. If the current limit for in-rush current is acceptable in application, do not use this feature. Used only when large bulk capacitance required on V
OUT
for
application.
I
SINK
= 500µA
V
IN
= 6V, PG = 6V
75
84
4
47
0.05
100
1
92
%V
OUT
%
mV
µA
5
FN6660.6
June 14, 2013
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