High Speed, Dual Channel, 6A, Power MOSFET Driver
With Programmable Delays
ISL89166, ISL89167, ISL89168
The ISL89166, ISL89167, and ISL89168 are high-speed, 6A,
dual channel MOSFET drivers. These parts are similar to the
ISL89160, ISL89161, ISL89162 drivers but use the NC pins for
programming the rising edge time delays of the outputs used for
dead time control.
As an alternative to using external RC circuits for time delays, the
programmable delays on the RDTA and RDTB pins allows the
user to delay the rising edge of the respective outputs just by
connecting an appropriate resistor value between these pins and
ground. The accuracy and temperature characteristics of the
time delays are specified freeing the user of the need to select
appropriate external resistors and capacitors that traditionally
are applied to the logic inputs to delay the output edges.
At high switching frequencies, these MOSFET drivers use very
little internal bias currents. Separate, non-overlapping drive
circuits are used to drive each CMOS output FET to prevent
shoot-thru currents in the output stage.
The start-up sequence is design to prevent unexpected glitches
when V
DD
is being turned on or turned off. When V
DD
< ~1V, an
internal 10kΩ resistor between the output and ground helps to
keep the output voltage low. When ~1V <V
DD
< UV, both outputs
are driven low with very low resistance and the logic inputs are
ignored. This insures that the driven FETs are off. When
V
DD
> UVLO, and after a short delay, the outputs now respond to
the logic inputs.
Features
• Typical ON-resistance <1Ω
• Specified Miller plateau drive currents
• Very low thermal impedance (θ
JC
= 3°C/W)
• Hysteretic Input logic levels for 3.3V CMOS, 5V CMOS, and TTL
• Precision threshold inputs for optional time delays with
external RC components
• Instead of RC components for time delays, a resistor can be
used to program delays
• 20ns rise and fall time driving a 10nF load.
• NC pins may be connected to ground or VDD for flexible PCB
layout options
Applications
• Synchronous Rectifier (SR) Driver
• Switch mode power supplies
• Motor Drives, Class D amplifiers, UPS, Inverters
• Pulse Transformer Driver
• Clock/Line Driver
350
V
DD
RDTA
1
INA
GND
INB
2
3
4
EPAD
8
7
6
5
OUTB
4.7µF
OUTA
RDTB
300
250
DELAY (ns)
200
150
+25°C (TYPICAL)
100
50
0
0
5
10
RDT (2k to 20k)
15
20
-40°C (WORST CASE)
+125°C (WORST CASE)
FIGURE 1. TYPICAL APPLICATION
FIGURE 2. PROGRAMMABLE TIME DELAYS
February 23, 2012
FN7720.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Copyright Intersil Americas Inc. 2011, 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL89166, ISL89167, ISL89168
Block Diagram
V
DD
For clarity, only one
channel is shown
The UV comparator holds off
the outputs until V
DD
~>
3.3VDC.
Separate FET drives, with
non-overlapping outputs,
prevent shoot-thru
currents in the output
CMOS FETs resulting with
very low operating
currents.
RDTx
RDTx
ISL89166
INx
rising
edge
delay
OUTx
10k
EPAD
For proper thermal and electrical
performance, the EPAD must be
connected to the PCB ground plane.
ISL89167,
ISL89168
GND
Pin Configurations
ISL89166FR, ISL89166FB
(8 LD TDFN, EPSOIC)
TOP VIEW
RDTA 1
INA 2
GND 3
INB 4
8 RDTB
7 OUTA
6 VDD
5 OUTB
Pin Descriptions
ISL89167FR, ISL89167FB
(8 LD TDFN, EPSOIC)
TOP VIEW
PIN
NUMBER
1
SYMBOL
RDTA
DESCRIPTION
Connect a resistor between this pin and
ground to program the rising edge delay of
OUTA, 0k to 20k
RDTA 1
/INA 2
GND 3
/INB 4
8 RDTB
7 OUTA
6 VDD
5 OUTB
2
3
4
5
INA or /INA Channel A input, 0V to VDD
GND
Power Ground, 0V
INB or /INB Channel B enable, 0V to VDD
OUTB
VDD
OUTA
RDTB
Channel B output
Power input, 4.5V to 16V
Channel A output, 0V to VDD
Connect a resistor between this pin and
ground to program the rising edge delay of
OUTB, 0k to 20k
Power Ground, 0V
ISL89168FR, ISL89168FB
(8 LD TDFN, EPSOIC)
TOP VIEW
RDTA 1
/INA 2
GND 3
INB 4
8 RDTB
7 OUTA
6 VDD
5 OUTB
6
7
8
EPAD
2
FN7720.1
February 23, 2012
ISL89166, ISL89167, ISL89168
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
ISL89166FRTAZ
ISL89167FRTAZ
ISL89168FRTAZ
ISL89166FRTBZ
ISL89167FRTBZ
ISL89168FRTBZ
ISL89166FRTCZ
ISL89167FRTCZ
ISL89168FRTCZ
ISL89166FBEAZ
ISL89167FBEAZ
ISL89168FBEAZ
ISL89166FBEBZ
ISL89167FBEBZ
ISL89168FBEBZ
ISL89166FBECZ
ISL89167FBECZ
ISL89168FBECZ
NOTES:
1. Add “-T*”, suffix for tape and reel. Please refer to
TB347
for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for
ISL89166, ISL89167, ISL89168.
For more information on MSL, please
see Technical Brief
TB363.
PART MARKING
166A
167A
168A
166B
167B
168B
166C
167C
168C
89166 FBEAZ
89167 FBEAZ
89168 FBEAZ
89166 FBEBZ
89167 FBEBZ
89168 FBEBZ
89166 FBECZ
89167 FBECZ
89168 FBECZ
TEMP RANGE (°C)
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
INPUT CONFIGURATION
non-inverting
inverting
inverting + non-inverting
non-inverting
inverting
inverting + non-inverting
non-inverting
inverting
inverting + non-inverting
non-inverting
inverting
inverting + non-inverting
non-inverting
inverting
inverting + non-inverting
non-inverting
inverting
inverting + non-inverting
PACKAGE
(Pb-Free)
8 Ld 3x3 TDFN
8 Ld 3x3 TDFN
8 Ld 3x3 TDFN
8 Ld 3x3 TDFN
8 Ld 3x3 TDFN
8 Ld 3x3 TDFN
8 Ld 3x3 TDFN
8 Ld 3x3 TDFN
8 Ld 3x3 TDFN
8 Ld EPSOIC
8 Ld EPSOIC
8 Ld EPSOIC
8 Ld EPSOIC
8 Ld EPSOIC
8 Ld EPSOIC
8 Ld EPSOIC
8 Ld EPSOIC
8 Ld EPSOIC
PKG.
DWG. #
L8.3x3I
L8.3x3I
L8.3x3I
L8.3x3I
L8.3x3I
L8.3x3I
L8.3x3I
L8.3x3I
L8.3x3I
M8.15D
M8.15D
M8.15D
M8.15D
M8.15D
M8.15D
M8.15D
M8.15D
M8.15D
3
FN7720.1
February 23, 2012
ISL89166, ISL89167, ISL89168
Absolute Maximum Ratings
Supply Voltage, V
DD
Relative to GND . . . . . . . . . . . . . . . . . . . . -0.3V to 18V
Logic Inputs (INA, INB) . . . . . . . . . . . . . . . . . . . . . . GND - 0.3v to V
DD
+ 0.3V
Outputs (OUTA, OUTB) . . . . . . . . . . . . . . . . . . . . . . GND - 0.3v to V
DD
+ 0.3V
Average Output Current (Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150mA
ESD Ratings
Human Body Model Class 2 (Tested per JESD22-A114E) . . . . . . . . 2000V
Machine Model Class B (Tested per JESD22-A115-A) . . . . . . . . . . . . 200V
Charged Device Model Class IV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500V
Latch-Up
(Tested per JESD-78B; Class 2, Level A)
Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mA
Thermal Information
Thermal Resistance (Typical)
θ
JA
(°C/W)
θ
JC
(°C/W)
8 Ld TDFN Package (Notes 4, 5). . . . . . . . .
44
3
8 Ld EPSOIC Package (Notes 4, 5) . . . . . . .
42
3
Max Power Dissipation at +25°C in Free Air . . . . . . . . . . . . . . . . . . . . . 2.27W
Max Power Dissipation at +25°C with Copper Plane . . . . . . . . . . . . . 33.3W
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Operating Junction Temp Range . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Maximum Recommended Operating
Conditions
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Supply Voltage, V
DD
Relative to GND. . . . . . . . . . . . . . . . . . . . . .4.5V to 16V
Logic Inputs (INA, INB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to V
DD
Outputs (OUTA, OUTB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to V
DD
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty
NOTES:
4.
θ
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379 for details.
5. For
θ
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
6. The average output current, when driving a power MOSFET or similar capacitive load, is the average of the rectified output current. The peak output
currents of this driver are self limiting by transconductance or r
DS(ON)
and do not required any external components to minimize the peaks. If the
output is driving a non-capacitive load, such as an LED, maximum output current must be limited by external means to less than the specified
absolute maximum.
DC Electrical Specifications
V
DD
= 12V, GND = 0V, No load on OUTA or OUTB, RDTA = RDTB = 0kΩ unless otherwise specified.
Boldface limits apply over the operating junction temperature range, -40°C to +125°C.
T
J
= +25°C
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
T
J
= -40°C to +125°C
MIN
(Note 7)
MAX
(Note 7)
UNITS
POWER SUPPLY
Voltage Range
V
DD
Quiescent Current
V
DD
I
DD
INx = GND
INA = INB = 1MHz, square wave
-
-
-
-
5
25
-
-
-
4.5
-
-
16
-
-
V
mA
mA
UNDERVOLTAGE
VDD Undervoltage Lock-out
(Note 9) (Figure 9)
Hysteresis
INPUTs
Input Range for INA, INB
Logic 0 Threshold
for INA, INB
Logic 1 Threshold
for INA, INB
Input Capacitance of
INA, INB (Note 8)
V
IN
V
IL
V
IH
C
IN
-
-
1.22
2.08
2
-
-
-
-
GND
1.12
1.98
-
V
DD
1.32
2.18
-
V
V
V
pF
V
UV
INA = INB = True (Note 10)
-
-
3.3
~25
-
-
-
-
-
-
V
mV
Nominally 37% x 3.3V
Nominally 63% x 3.3V
-
-
-
4
FN7720.1
February 23, 2012
ISL89166, ISL89167, ISL89168
DC Electrical Specifications
V
DD
= 12V, GND = 0V, No load on OUTA or OUTB, RDTA = RDTB = 0kΩ unless otherwise specified.
Boldface limits apply over the operating junction temperature range, -40°C to +125°C.
(Continued)
T
J
= +25°C
PARAMETERS
Input Bias Current
for INA, INB
SYMBOL
I
IN
TEST CONDITIONS
GND < V
IN
< V
DD
MIN
-
TYP
-
MAX
-
T
J
= -40°C to +125°C
MIN
(Note 7)
-10
MAX
(Note 7)
+10
UNITS
µA
OUTPUTS
High Level Output Voltage
Low Level Output Voltage
Peak Output Source Current
Peak Output Sink Current
NOTES:
7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
8. This parameter is taken from the simulation models for the input FET. The actual capacitance on this input will be dominated by the PCB parasitic
capacitance.
9. A 400µs delay further inhibits the release of the output state when the UV positive going threshold is crossed. See Figure 9
10. The true state of a specific part number is defined by the input logic symbol.
V
OHA
V
OHB
V
OLA
V
OLB
I
O
I
O
V
O
(initial) = 0V, C
LOAD
= 10nF
V
O
(initial) = 12V, C
LOAD
= 10nF
-
-
-
-
-
-
-6
+6
-
-
-
-
V
DD
- 0.1
GND
-
-
V
DD
GND + 0.1
-
-
V
V
A
A
AC Electrical Specifications
Specified.
Boldface limits apply over the operating junction temperature range, -40°C to +125°C.
V
DD
= 12V, GND = 0V, No Load on OUTA or OUTB, RDTA = RDTB = 0kΩ unless Otherwise
T
J
= +25°C
T
J
= -40°C to +125°C
MAX
-
-
-
-
-
-
-
-
-
-
-
MIN
(Note 7)
-
-
-
-
-
-
237
29
-
-
-
MAX
(Note 7)
40
40
50
50
-
-
297
58
-
-
-
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
A
A
A
PARAMETERS
Output Rise Time (see Figure 4)
Output Fall Time (see Figure 4)
Output Rising Edge Propagation Delay (see Figure 3)
Output Falling Edge Propagation Delay (see Figure 3)
(Note 12)
Rising Propagation Matching (see Figure 3)
Falling Propagation Matching (see Figure 3)
Rising edge timer delay (Note 11)
SYMBOL
t
R
t
F
t
RDLY
t
FDLY
t
RM
t
FM
t
RTDLY20
TEST CONDITIONS
/NOTES
C
LOAD
= 10nF,
10% to 90%
C
LOAD
= 10nF,
90% to 10%
RDTx = 0kΩ
RDTx = 0kΩ
RDTx = 0kΩ
RDTx = 0kΩ
RTx = 20kΩ,
No load
RTx = 2.0kΩ, No
load
V
DD
= 10V,
V
MILLER
= 5V
V
DD
= 10V,
V
MILLER
= 3V
V
DD
= 10V,
V
MILLER
= 2V
MIN
-
-
-
-
-
-
-
-
-
-
-
TYP
20
20
25
25
<1ns
<1ns
266
42
6
4.7
3.7
t
RTDLY2
Miller Plateau Sink Current
(See Test Circuit Figure 5)
-I
MP
-I
MP
-I
MP
5
FN7720.1
February 23, 2012
DSP 与 ARM 处理器
