CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
5.
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief
TB379
for details.
6. For
JC
, the “case temp” location is taken at the package top center.
Analog Specifications
Over recommended operating conditions, unless otherwise stated.
SYMBOL
R
TOTAL
PARAMETER
R
H
to R
L
Resistance
W option
U option
R
H
to R
L
Resistance Tolerance
R
W
C
H
/C
L
/C
W
I
LkgDCP
Wiper Resistance
Potentiometer Capacitance
Leakage on DCP Pins
Voltage at pin from GND to V
CC
V
CC
= 3.3V @ +25°C
-20
85
10/10/25
0.1
TEST CONDITIONS
MIN
TYP
MAX
(Note 19) (Note 7) (Note 19)
10
50
+20
200
UNIT
k
k
%
pF
µA
VOLTAGE DIVIDER MODE
INL
DNL
Integral Non-linearity
Differential Non-linearity
Monotonic over all tap positions
W option
U option
ZS
error
(Note 9)
FS
error
(Note 10)
Zero-scale Error
W option
U option
Full-scale Error
W option
U option
DCP Register set to 80 hex
-1
-1
-1
0
0
-3
-1
±0.2
±0.1
±0.1
1
0.5
-1
-0.5
±15
1
1
1
3
1
0
0
LSB
(Note 8)
LSB
(Note 8)
LSB
(Note 8)
LSB
(Note 8)
LSB
(Note 8)
ppm/°C
TC
V
(Note 16) Ratiometric Temperature Coefficient
RESISTOR MODE
R
INL
(Note 14)
R
DNL
(Note 13)
Integral Non-linearity
Differential Non-linearity
DCP register set between 20 hex and FF hex.
Monotonic over all tap positions
W option
DCP register set between 20 hex
and FF hex. Monotonic over all tap
positions
U option
W option
U option
-2
-1
-1
0
0
±0.25
±0.1
±0.1
1
0.5
±45
2
1
1
3
1
MI
(Note 11)
MI
(Note 11)
MI
(Note 11)
MI
(Note 11)
MI
(Note 11)
ppm/°C
R
OFFSET
(Note 12)
Offset
TC
R
Resistance Temperature Coefficient
(Notes 15, 16)
DCP register set between 20 hex and FF hex
FN8247 Rev 8.00
May 10, 2012
Page 3 of 8
ISL90727, ISL90728
Operating Specifications
SYMBOL
I
CC1
I
SB
I
ComLkg
PARAMETER
V
CC
Supply Current
(Volatile write/read)
V
CC
Current (standby)
Common-Mode Leakage
TEST CONDITIONS
f
SCL
= 400kHz; SDA = Open; (for I
2
C, Active,
Read and Volatile Write States only)
V
CC
= +5.5V, I
2
C Interface in Standby State
Voltage at SDA pin to GND or V
CC
SCL falling edge of last bit of DCP Data Byte to
wiper change
0.2
V
CC
above V
POR
, to DCP Initial Value Register
recall completed, and I
2
C Interface in standby state
3
500
MIN
TYP
MAX
(Note 19) (Note 7) (Note 19) UNIT
200
500
3
µA
nA
µA
ns
V/ms
ms
t
DCP
(Note 16) DCP Wiper Response Time
V
CC
Ramp
(Note 20)
t
D
V
CC
Ramp Rate
Power-up Delay
SERIAL INTERFACE SPECIFICATIONS
V
IL
V
IH
Hysteresis
V
OL
SDA, and SCL Input Buffer LOW
Voltage
SDA, and SCL Input Buffer HIGH
Voltage
SDA and SCL Input Buffer Hysteresis
SDA Output Buffer LOW Voltage,
Sinking 4mA
(Note 17)
(Note 17)
-0.3
0.7*
V
CC
0.05*
V
CC
0
0.4
10
400
Any pulse narrower than the max spec is
suppressed.
50
900
1300
0.3*
V
CC
V
CC
+
0.3
V
V
V
V
pF
kHz
ns
ns
ns
Cpin (Note 18) SDA and SCL Pin Capacitance
f
SCL
t
IN
t
AA
t
BUF
SCL Frequency
Pulse Width Suppression Time at
SDA and SCL Inputs
SCL Falling Edge to SDA Output Data SCL falling edge crossing 30% of V
CC
, until SDA
Valid
exits the 30% to 70% of V
CC
window.
Time the Bus Must be Free Before the SDA crossing 70% of V
CC
during a STOP
Start of a New Transmission
condition, to SDA crossing 70% of V
CC
during
the following START condition.
Clock LOW Time
Clock HIGH Time
START Condition Setup Time
START Condition Hold Time
Input Data Setup Time
Input Data Hold Time
STOP Condition Setup Time
STOP Condition Hold Time for Read,
or Volatile Only Write
Output Data Hold Time
SDA and SCL Rise Time
Measured at the 30% of V
CC
crossing.
Measured at the 70% of V
CC
crossing.
SCL rising edge to SDA falling edge. Both
crossing 70% of V
CC
.
From SDA falling edge crossing 30% of V
CC
to
SCL falling edge crossing 70% of V
CC
.
From SDA exiting the 30% to 70% of V
CC
window, to SCL rising edge crossing 30% of V
CC
From SCL rising edge crossing 70% of V
CC
to
SDA entering the 30% to 70% of V
CC
window.
From SCL rising edge crossing 70% of V
CC
, to
SDA rising edge crossing 30% of V
CC
.
From SDA rising edge to SCL falling edge. Both
crossing 70% of V
CC
.
From SCL falling edge crossing 30% of V
CC
,
until SDA enters the 30% to 70% of V
CC
window.
From 30% to 70% of V
CC
t
LOW
t
HIGH
t
SU:STA
t
HD:STA
t
SU:DAT
t
HD:DAT
t
SU:STO
t
HD:STO
t
DH
t
R
(Note 18)
1300
600
600
600
100
0
600
600
0
20 +
0.1*Cb
250
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
FN8247 Rev 8.00
May 10, 2012
Page 4 of 8
ISL90727, ISL90728
Operating Specifications
SYMBOL
t
F
(Note 18)
Cb (Note 18)
Rpu (Note 18)
(Continued)
TEST CONDITIONS
From 70% to 30% of V
CC
Total on-chip and off-chip
Maximum is determined by t
R
and t
F
.
For Cb = 400pF, max is about 2k~ 2.5k.
For Cb = 40pF, max is about 15k~ 20k
MIN
TYP
MAX
(Note 19) (Note 7) (Note 19) UNIT
20 +
0.1*Cb
10
1
250
400
ns
pF
k
PARAMETER
SDA and SCL Fall Time
Capacitive Loading of SDA or SCL
SDA and SCL Bus Pull-up Resistor
Off-chip
NOTES:
7. Typical values are for T
A
= +25°C and 3.3V supply voltage.
8. LSB: [V(R
W
)
127
– V(R
W
)
0
]
/
127. V(R
W
)
127
and V(R
W
)
0
are V(R
W
) for the DCP register set to FF hex and 00 hex respectively. LSB is the
incremental voltage when changing from one tap to an adjacent tap.
9. ZS error = V(R
W
)
0
/
LSB.
10. FS error = [V(R
W
)
127
– V
CC
]
/
LSB.
11. MI =
|
R
127
– R
0
|
/
127. R
127
and R
0
are the measured resistances for the DCP register set to FF hex and 00 hex respectively.
