Ambient Temperature Range . . . . . . . . . . . . . . . . . . .-25°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1.
θ
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2.
θ
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
3. For
θ
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Unless otherwise noted, all parameters are established over the operational supply voltage and temperature
range of the device as follows: T
A
= -25°C to +85°C; V
DD
= 2.6V to 4.8V; Parameters with MIN and/or MAX
limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
PARAMETER
DC CHARACTERISTICS
Supply Voltage
V
DD
During normal operation
During OTP ROM programming
2.6
2.8
-
-
-
-
38
40
5.0
4.8
4.8
55
65
8.0
0.5
500
2.7
13
2.4
2.1
V
V
µA
µA
µA
µA
µA
V
V
V
V
Run Mode Supply Current
(Exclude I/O Current)
I
DD
V
DD
= 4.2V
V
DD
= 4.8V
V
DD
= 1.5V
Sleep Mode Supply Current
OTP Programming Mode Supply Current
Internal Regulated Supply Voltage
Internal OTP ROM Programming Voltage
POR Release Threshold
POR Assertion Threshold
XSD PIN CHARACTERISTICS
XSD Input Low Voltage
XSD Input High Voltage
XSD Input Hysteresis
XSD Internal Pull-down Current
I
DDS
I
DDP
V
RG
V
PP
V
POR+
V
POR-
V
DD
= 4.2V, XSD pin floating
For ~ 1.8ms duration per write operation
Observable only in test mode
Observable only in test mode
-
-
2.3
11
1.9
1.5
0.15
250
2.5
12
2.2
1.8
V
IL
V
IH
V
HYS
I
PD
V
DD
= 2.6V
V
DD
= 4.2V
V
DD
= 4.8V
-0.4
1.5
-
-
-
-
-
-
-
-
-
-
400
0.8
1.2
1.8
-
-
-
6
0.5
V
DD
+ 0.4V
-
-
2.0
2.5
0.4
2
50
-
V
V
mV
µA
µA
µA
V
µs
ns
pF
XSD Output Low Voltage
XSD Input Transition Time
XSD Output Fall Time
XSD Pin Capacitance
V
OL
t
X
t
F
C
PIN
I
OL
= 1mA
10% to 90% transition time
90% to 10%, C
LOAD
= 12pF
2
FN6651.1
July 30, 2008
ISL9206A
Electrical Specifications
Unless otherwise noted, all parameters are established over the operational supply voltage and temperature
range of the device as follows: T
A
= -25°C to +85°C; V
DD
= 2.6V to 4.8V; Parameters with MIN and/or MAX
limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
(Continued)
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
PARAMETER
XSD BUS TIMING CHARACTERISTICS
(Refer to XSD Bus Symbol Timing Definitions Tables beginning on page 8)
Programming Bit Rate
XSD Input De-glitch Time
Device Wake-up Time
Device Sleep Wait Time
Auto-Sleep Time-out Period
OTP ROM Write Time
Hash Calculation Time
t
WDG
t
WKE
t
SLP
t
ASLP
t
EEW
t
HASH
x = 0.5 to 4
Pulse width narrower than the de-glitch time will not
cause the device to wake up
From falling-edge of break command issued by host to
falling-edge of break command returned by device
From when the ‘11’ Opcode is detected to the shut-off
of the internal regulator
From the last transition detected on the XSD bus to the
device going into sleep mode
From the last BT of the 2nd write data frame to when
device is ready to accept the next instruction
From the last BT of the Challenge Code Word from the
host to the Authentication Code being available for
read
From the last BT of the Soft-Reset instruction issued
by the host to the falling-edge of break command
returned by device
2.89
7
130
4
-
-
-
-
-
160
-
1
1.8
1
23.12
20
200
-
-
1.9
-
kHz
µs
µs
µs
s
ms
BT
Soft-Reset Time
t
SRST
-
-
30
µs
Pin Descriptions
SOT-23
PIN NUMBER
1
2
3
4
5
TDFN
PIN NUMBER
1
2, 3, 6, 7
4
5
8
PIN NAME
VSS
NC
VDD
TIO
XSD
System ground.
No connection.
Supply voltage.
Production test I/O pin. Used only during production testing. Must be left floating during
normal operation.
Communication bus with weak internal pull-down to VSS. This pin is a Schmitt-trigger input
and an open-drain output. An appropriate pull-up resistor is required on the host side.
DESCRIPTION
3
FN6651.1
July 30, 2008
ISL9206A
Typical Applications
PACK+
R1
100Ω XSD
D1
5.1V
PACK-
R2
100Ω
PROTECTION
C1
0.1µF
XSD
ISL9206A
VSS
VDD
+
FIGURE 1. TYPICAL APPLICATION WITH THE ISL9206A POWERED BY THE BATTERY
PACK+
R1
100Ω XSD
D1
5.1V
PACK-
XSD
ISL9206A
VSS
VDD
C1
0.1µF
PROTECTION
+
FIGURE 2. TYPICAL APPLICATION WITH THE ISL9206A POWERED BY THE XSD BUS
Block Diagram
VDD
ESD DIODE
POR/2.5V
REGULATOR
OSCILLATOR
ANALOG
DIGITAL
XSD
XSD
COMM
INTERFACE
DCFG (1 BYTE)
DTRM (1 BYTE)
SECRET #1
(4 BYTES)
SECRET #2
(4 BYTES)
SECRET #3
(4 BYTES)
GENERAL PURPOSE
(2 BYTES)
16 BYTES
OTPROM
CONTROL/STATUS/
TEST INTERFACE
AUTH
SESL
CHLG
FLEXIHASH+™
ENGINE
ESD DIODE
MSCR
STAT
TIO
VSS
FIGURE 3. FUNCTIONAL BLOCK DIAGRAM
4
FN6651.1
July 30, 2008
ISL9206A
Theory of Operation
The ISL9206A contains all circuitry required to support
battery pack authentication based on a challenge-response
scheme. It provides a 16-Byte One-Time Programmable
Read-Only Memory (OTPROM) space for the storage of up
to 96-Bit of secret for the authentication and other user
information. A 32-Bit hash engine (FlexiHash+™) calculates
the authentication result immediately after receiving a 32-Bit
random challenge code. The communication between the
ISL9206A and the host is implemented through the XSD
single-wire communication bus.
Major functions within the ISL9206A include the following, as
shown in Figure 3.
• Power-on reset (POR) and a 2.5V regulator to power all
internal logic circuits.
• 16x8-Bit (16-Byte) OTP ROM, as shown in Table 8. The
first part (two bytes) contains the device default
configuration (DCFG) information (such as the device
address and the XSD communication speed) and the
default trimming (DTRM) information (such as the internal
oscillator frequency trimming). The second part contains
two groups (12-Byte) of memory that can be
independently locked out for the storage of up to three
sets of secret. The last part provides two additional bytes
of space for general-purpose information.
• Control functions, including master control (MSCR) and
status (STAT) registers (as shown in Table 9), interrupt
generation, and the test-related interface.
• FlexiHash+™ engine that includes the 32-Bit highly
