DATASHEET
ISL94202
Series Charge/Discharge Path 3-to-8 Cell Li-Ion Battery Pack Monitor
FN8889
Rev.2.00
Mar 8, 2017
1.
Overview
The
ISL94202
is a Li-ion battery monitor IC that supports from three to eight series connected cells. It provides complete
battery monitoring and pack control. The ISL94202 provides automatic shutdown and recovery from out-of-bounds conditions
and automatically controls pack cell balancing.
The ISL94202 is highly configurable as a stand-alone unit, but can be used with an external microcontroller, which
communicates to the IC through an I
2
C interface.
1.1
Features
• Eight cell voltage monitors support Li-ion CoO
2
, Li-ion Mn
2
O
4
, and Li-ion FePO
4
chemistries
• Stand-alone pack control - no microcontroller needed
• Multiple voltage protection options (each programmable to 4.8V; 12-bit digital value) and selectable overcurrent
protection levels
• Programmable detection/recovery times for overvoltage, undervoltage, overcurrent, and short-circuit conditions
• Configuration/calibration registers maintained in EEPROM
• Open battery connect detection
• Integrated charge/discharge FET drive circuitry with built-in charge pump supports high-side N-channel FETs
• Cell balancing uses external FETs with internal state machine or external microcontroller
• Enters low power states after periods of inactivity
• Charge or discharge current detection resumes normal scan rates
1.2
Applications
• Power tools
• Battery back-up systems
• Light electric vehicles
• Portable equipment
• Energy storage systems
• Solar farms
• Medical equipment
• Hospital beds
• Monitoring equipment
• Ventilators
1.3
Related Literature
•
ISL94202
product page
• For a full list of related documents, visit our website
FN8889 Rev.2.00
Mar 8, 2017
Page 1 of
89
ISL94202
1. Overview
1.4
Typical Application Diagram
P+
43V
43V
CFET
DFET
VBATT
VC8
CB8
VC7
CB7
VC6
CB6
VC5
CB5
VC4
CB4
VC3
CB3
VC2
CB2
VC1
CB1
VC0
GND
VSS
PSD
FETSOFF
INT
RGO
CHRG
ISL94202
SD
EOC
SCL
SDA
TEMPO
xT1
xT2
VREF
ADDR
P-
Figure 1.1
Typical Application Diagram
CHMON
PCFET
LDMON
VDD
C1
CS1
CS2
C2
C3
FN8889 Rev.2.00
Mar 8, 2017
Page 2 of
89
ISL94202
1. Overview
1.5
Block Diagram
N-CHANNEL FETs
P+
PACK+
VDD
+16V
PCFET
CFET
VDD
DFET
CS1
CS2
VDD
+16V
C1
C2
C3
LDMON
CHMON
100Ω
470nF
BAT+
1kΩ
330kΩ
47nF
10kΩ
1kΩ
330kΩ
47nF
10kΩ
1kΩ
330kΩ
47nF
10kΩ
1kΩ
47nF
10kΩ
330kΩ
1kΩ
47nF
10kΩ
330kΩ
1kΩ
47nF
10kΩ
330kΩ
1kΩ
47nF
10kΩ
330kΩ
1kΩ
47nF
10kΩ
330kΩ
BAT-
V
SS
CB1
CB2
CB4
CB5
CB8
CURRENT-SENSE GAIN AMPLIFIER
x5/x50/x500 GAIN
OVERCURRENT STATE MACHINE
VBATT
VC8
FET CONTROLS/CHARGE PUMP
O.C.
WAKEUP
RECOVERY CIRCUIT
POWER-ON
RESET STATE
MACHINE
EOC
VSS
SD
VSS
FETSOFF
PSD
EOC/SD
ERROR CONDITIONS
(OV, UV, SLP STATE MACHINES)
VC7
CB8:1
CB STATE
MACHINE
CB7
VC6
RAM
INPUT BUFFER/LEVEL SHIFTER/OPEN WIRE DETECT
CB6
VC5
EEPROM
REGISTERS
INT
TEMP/VOLTAGE
MONITOR ALU
VC4
OSC
TIMING
AND
CONTROL
SCAN STATE
MACHINE
MEMORY
MANAGER
SCAN STATE
CB STATE
OVERCURRENT STATE
EOC/SD/ERROR STATE
LDO
RGO
REG
RGO (OUT)
VC3
CB3
VC2
I
2
C
SDAO
SDAI
SCL
ADDR
MUX
TEMPO
WATCHDOG TIMER
xT2
xT2
xT1
VC1
MUX
TEMP
VB/16
RGO/2
TEMP
T
GAIN
x1/x2
VREF
MUX
14-BIT
ADC
xT1
iT
VC0
VREF
PACK-
P-
Figure 1.2
Block Diagram
FN8889 Rev.2.00
Mar 8, 2017
Page 3 of
89
ISL94202
1. Overview
1.6
Ordering Information
Part Number
(Notes
1 2, 3)
Part
Marking
94202 IRTZ
Evaluation Kit
Temp. Range
(°C)
-40 to +85
Package
(RoHS Compliant)
48 Ld TQFN
Pkg.
Dwg. #
L48.6x6
ISL94202IRTZ
ISL94202EVKIT1Z
Notes:
1. Add “-T” suffix for 4k unit, “-T7” for 1k unit, or “-T7A” suffix for 250 unit tape and reel options. Refer to
TB347
for details on
reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures
that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), see product information page for
ISL94202.
For more information on MSL, see tech
brief
TB363.
Table 1.1
Key Differences Between Family of Parts
Pack
Voltage
(Op)
Min Max
(V) (V)
4
4
8
6
36
36
Cell
Current
Balance Sense
High
Side
High
Side
Low
Side
No
Charge/Discharge FET
Supply Current
(Typ)
Stand-
Internal Daisy
Alone
ADC
Chain
Capable
Yes
Yes
No
No
Yes
Yes
No
Yes
No
No
No
Yes
Part #
Cells
Supported
Min Max
Control Arrangement Location Normal Sleep
External
External
Yes
Yes
Yes
No
One Path
Two Path
Both
N/A
High
Side
High
Side
Low Side
N/A
348µA
348µA
850µA
13µA
13µA
2µA
ISL94202
ISL94203
ISL94208
ISL94212
3
3
4
6
8
8
6
12
26.4 Internal
60
External
3.31mA 12µA
FN8889 Rev.2.00
Mar 8, 2017
Page 4 of
89
ISL94202
1. Overview
1.7
Pin Configuration
ISL94202
(48 LD TQFN)
TOP VIEW
CHMON
37
36 RGO
35 EOC
34 SD
33 FETSOFF
32 PSD
PAD
(GND)
31 INT
30 DNC
29 VSS
28 VSS
27 SDAO
26 SDAI
25 SCL
13
VC2
14
CB2
15
VC1
16
CB1
17
VC0
18
VSS
19
VREF
20
XT1
21
XT2
22
TEMPO
23
DNC
24
ADDR
LDMON
38
PCFET
VBATT
CFET
DFET
CSI1
CSI2
VDD
C1
C2
40
48
VC8
CB8
VC7
CB7
VC6
CB6
VC5
CB5
VC4
1
2
3
4
5
6
7
8
9
47
46
45
44
43
42
41
CB4 10
VC3
11
CB3 12
C3
39
FN8889 Rev.2.00
Mar 8, 2017
Page 5 of
89
