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ispLSI 2064VL
2.5V In-System Programmable
SuperFAST™ High Density PLD
Features
• SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC
— 2000 PLD Gates
— 64 and 32 I/O Pin Versions, Four Dedicated Inputs
— 64 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— 100% Functional, JEDEC and Pinout Compatible with
ispLSI 2064V and 2064VE Devices
2.5V LOW VOLTAGE 2064 ARCHITECTURE
— Interfaces with Standard 3.3V TTL Devices (Inputs
and I/Os are 3.3V Tolerant)
— 60 mA Typical Active Current
HIGH-PERFORMANCE E
2
CMOS
®
TECHNOLOGY
—
f
max
= 165MHz Maximum Operating Frequency
—
t
pd
= 5.5ns Propagation Delay
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
IN-SYSTEM PROGRAMMABLE
— 2.5V In-System Programmability (ISP™) Using
Boundary Scan Test Access Port (TAP)
— Open-Drain Output Option for Flexible Bus Interface
Capability, Allowing Easy Implementation of Wired-OR
or Bus Arbitration Logic
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
100% IEEE 1149.1 BOUNDARY SCAN TESTABLE
Input Bus
®
Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability.
www.latticesemi.com/sales/discontinueddevicessales.cfm
Functional Block Diagram
Output Routing Pool (ORP)
B7
B6
B5
B4
A0
Output Routing Pool (ORP)
•
Input Bus
A2
GLB
Logic
Array
D Q
D Q
B1
D Q
A3
A4
A5
A6
A7
B0
•
Output Routing Pool (ORP)
Input Bus
0139A/2064VL
•
Description
The ispLSI 2064VL is a High Density Programmable
Logic Device available in 64 and 32 I/O-pin versions. The
device contains 64 Registers, four Dedicated Input pins,
three Dedicated Clock Input pins, two dedicated Global
OE input pins and a Global Routing Pool (GRP). The
GRP provides complete interconnectivity between all of
these elements. The ispLSI 2064VL features in-system
programmability through the Boundary Scan Test Ac-
cess Port (TAP) and is 100% IEEE 1149.1 Boundary
Scan Testable. The ispLSI 2064VL offers non-volatile
reprogrammability of the logic, as well as the intercon-
nect, to provide truly reconfigurable systems.
The basic unit of logic on the ispLSI 2064VL device is the
Generic Logic Block (GLB). The GLBs are labeled A0,
A1…B7 (see Figure 1). There are a total of 16 GLBs in the
ispLSI 2064VL device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
•
• THE EASE OF USE AND FAST SYSTEM SPEED OF
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
Copyright © 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
January 2002
2064vl_03
1
Input Bus
A1
D Q
B2
Output Routing Pool (ORP)
Global Routing Pool
(GRP)
B3
Specifications
ispLSI 2064VL
Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability.
www.latticesemi.com/sales/discontinueddevicessales.cfm
Functional Block Diagram
Figure 1. ispLSI 2064VL Functional Block Diagram (64-I/O and 32-I/O Versions)
GOE 0
GOE 1
I/O 63
I/O 62
I/O 61
I/O 60
I/O 59
I/O 58
I/O 57
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
I/O 31
I/O 30
I/O 29
I/O 28
Input Bus
Generic Logic
Blocks (GLBs)
I/O 27
I/O 26
I/O 25
I/O 24
Input Bus
Generic Logic
Blocks (GLBs)
Megablock
B7
Output Routing Pool (ORP)
B6
B5
B4
Megablock
B7
Output Routing Pool (ORP)
B6
B5
B4
Output Routing Pool (ORP)
Output Routing Pool (ORP)
Output Routing Pool (ORP)
Input Bus
Input Bus
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
TDI/IN 0
TMS/IN 1
A2
B1
I/O 39
I/O 38
I/O 37
I/O 36
I/O 35
I/O 34
I/O 33
I/O 32
TCK/IN 3
TDO/IN 2
Input Bus
A2
B1
A3
B0
I/O 4
I/O 5
I/O 6
I/O 7
TDI/IN 0
TDO/IN 1
Input Bus
I/O 4
I/O 5
I/O 6
I/O 7
A1
Global Routing Pool
(GRP)
B2
I/O 43
I/O 42
I/O 41
I/O 40
A1
Global Routing Pool
(GRP)
B2
Output Routing Pool (ORP)
I/O 0
I/O 1
I/O 2
I/O 3
I/O 47
A0
B3
I/O 46
I/O 45
I/O 44
I/O 0
I/O 1
I/O 2
I/O 3
I/O 23
A0
B3
I/O 22
I/O 21
I/O 20
A3
B0
I/O 19
I/O 18
I/O 17
I/O 16
GOE0/IN 3
A4
A5
A6
A7
A4
A5
A6
A7
TMS/IN 2
CLK 0
CLK 1
CLK 2
BSCAN
Input Bus
BSCAN
Input Bus
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
Y0
Y1
Y2
The 64-I/O 2064VL contains 64 I/O cells, while the 32-
I/O version contains 32 I/O cells. Each I/O cell is directly
connected to an I/O pin and can be individually pro-
grammed to be a combinatorial input, output or
bi-directional I/O pin with 3-state control and the output
drivers can source 4 mA or sink 8 mA. Each output can
be programmed independently for fast or slow output
slew rate to minimize overall output switching noise.
Device pins can be safely driven to 3.3V signal levels to
support mixed-voltage systems.
Eight GLBs, 32 or 16 I/O cells, two dedicated inputs and
two or one ORPs are connected together to make a
Megablock (see Figure 1). The outputs of the eight GLBs
are connected to a set of 32 or 16 universal I/O cells by
two or one ORPs. Each ispLSI 2064VL device contains
two Megablocks.
The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 2064VL device are selected using
the dedicated clock pins. Three dedicated clock pins (Y0,
Y1, Y2) or an asynchronous clock can be selected on a
GLB basis. The asynchronous or Product Term clock can
be generated in any GLB for its own clock.
Programmable Open-Drain Outputs
In addition to the standard output configuration, the
outputs of the ispLSI 2064VL are individually program-
mable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a pro-
grammable fuse. The default configuration is totem-pole
configuration. The open-drain/totem-pole option is se-
lectable through the Lattice software tools.
2
GOE1/Y0
RESET/Y1
TCK/Y2
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
0139B/2064VL
CLK 0
CLK 1
CLK 2
0139B/2064VL.32IO
RESET
Output Routing Pool (ORP)
Output Routing Pool (ORP)
Specifications
ispLSI 2064VL
Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability.
www.latticesemi.com/sales/discontinueddevicessales.cfm
Absolute Maximum Ratings
1
Supply Voltage V
cc .................................................
-0.5 to +4.05V
Input Voltage Applied ................................... -0.5 to +4.05V
Off-State Output Voltage Applied ................ -0.5 to +4.05V
Storage Temperature ..................................... -65 to 150°C
Case Temp. with Power Applied .................... -55 to 125°C
Max. Junction Temp. (T
J
) with Power Applied ............ 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Condition
SYMBOL
PARAMETER
Supply Voltage
Input Low Voltage
Input High Voltage
Commercial
Industrial
T
A
= 0°C to + 70°C
T
A
= -40°C to + 85°C
MIN.
2.3
2.3
-0.3
1.7
MAX.
2.7
2.7
0.7
3.6
UNITS
V
V
V
V
V
CC
V
IL
V
IH
Table 2-0005/2064VL
Capacitance (TA=25°C, f=1.0 MHz)
SYMBOL
PARAMETER
Dedicated Input Capacitance
I/O Capacitance
Clock and Global Output Enable Capacitance
TYPICAL
8
6
10
UNITS
pf
pf
pf
TEST CONDITIONS
V
CC
= 2.5V, V
IN
= 0.0V
V
CC
= 2.5V, V
I/O
= 0.0V
V
CC
= 2.5V, V
Y
= 0.0V
Table 2-0006/2064VL
C
1
C
2
C
3
Erase Reprogram Specifications
PARAMETER
Erase/Reprogram Cycles
MINIMUM
10,000
MAXIMUM
—
UNITS
Cycles
Table 2-0008/2064VL
3
Specifications
ispLSI 2064VL
Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability.
www.latticesemi.com/sales/discontinueddevicessales.cfm
Switching Test Conditions
Input Pulse Levels
Input Rise and Fall Time
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
3-state levels are measured 0.15V from
steady-state active level.
GND to V
CC
≤
1.5 ns 10% to 90%
V
CC
/2
V
CC
/2
See Figure 2
Table 2-0003/2064VL
Figure 2. Test Load
V
CC
R1
Device
Output
R2
CL
*
Test
Point
Output Load Conditions (see Figure 2)
TEST CONDITION
A
B
Active High
Active Low
Active High to Z
at
V
OH
-0.15V
Active Low to Z
at
V
OL
+0.15V
R1
250Ω
R2
218Ω
218Ω
CL
35pF
35pF
35pF
5pF
5pF
*
CL includes Test Fixture and Probe Capacitance.
0213A/2064VL
∞
250Ω
∞
218Ω
∞
250Ω
C
∞
Table 2-0004/2064VL
DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL
PARAMETER
Output Low Voltage
CONDITION
I
OL
= 100µA
I
OL
= 8mA
I
OH
= -100µA
Output High Voltage
Input or I/O Low Leakage Current
Input or I/O High Leakage Current
BSCAN
Input Pull-Up Current
I/O Active Pull-Up Current
Output Short Circuit Current
Operating Power Supply Current
I
OH
= -1mA
I
OH
= -4mA
0V
≤
V
IN
≤
V
IL
(Max.)
V
IH
(min)
≤
V
IN
≤
3.6V
0V
≤
V
IN
≤
V
IL
0V
≤
V
IN
≤
V
IL
V
CC
= 2.5V, V
OUT
= 0.5V
V
IL
= 0.0V, V
IH
= 2.5V
f
CLK
= 1 MHz
Table 2-0007/2064VL
1. One output at a time for a maximum duration of one second. V
OUT
= 0.5V was selected to avoid test
problems by tester ground degradation. Characterized but not 100% tested.
2. Measured using four 16-bit counters.
3. Typical values are at V
CC
= 2.5V and T
A
= 25°C.
4. Maximum I
CC
varies widely with specific device configuration and operating frequency. Refer to Power Consumption
section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to
estimate maximum I
CC
.
5. With no pull-up resistors.
MIN.
—
—
V
CC
- 0.2
TYP.
—
—
—
—
—
—
—
—
—
—
60
3
MAX. UNITS
0.2
0.4
—
—
—
-10
10
-150
-150
-100
—
V
V
V
V
V
µA
µA
µA
µA
mA
mA
V
OL
V
OH
I
IL
5
I
IH
I
IL-isp
I
IL-PU
I
OS
1
I
CC
2, 4
2.0
1.8
—
—
—
—
—
—
4
