IXDF504 / IXDI504 / IXDN504
4 Ampere Dual Low-Side Ultrafast MOSFET Drivers
Features
• Built using the advantages and compatibility
of CMOS and IXYS HDMOS
TM
processes
• Latch-Up Protected up to 4 Amps
• High Peak Output Current: 4A Peak
• Wide Operating Range: 4.5V to 30V
•
-55°C
to +125°C Extended Operating
Temperature
• High Capacitive Load
Drive Capability: 1800pF in <15ns
• Matched Rise And Fall Times
• Low Propagation Delay Time
• Low Output Impedance
• Low Supply Current
• Two Drivers in Single Chip
General Description
The IXDF504, IXDI504 and IXDN504 each consist of two 4-
Amp CMOS high speed MOSFET Gate Drivers for driving
the latest IXYS MOSFETs & IGBTs. Each of the outputs
can source and sink 4 Amps of Peak Current while produc-
ing voltage rise and fall times of less than 15ns. The input
of each driver is TTL or CMOS compatible and is virtually
immune to latch up. Patented* design innovations eliminate
cross conduction and current "shoot-through". Improved
speed and drive capabilities are further enhanced by very
fast, matched rise and fall times.
The IXDF504 is configured with one Gate Driver Inverting +
one Gate Driver Non-Inverting. The IXDI504 is configured as
a Dual Inverting Gate Driver, and the IXDN504 is configured
as a Dual Non-Inverting Gate Driver.
The IXDF504, IXDI504 and IXDN504 are each available in
the 8-Pin P-DIP (PI) package, the 8-Pin SOIC (SIA) pack-
age, and the 6-Lead DFN (D1) package, (which occupies
less than 65% of the board area of the 8-Pin SOIC).
Applications
•
•
•
•
•
•
•
•
•
•
Driving MOSFETs and IGBTs
Motor Controls
Line Drivers
Pulse Generators
Local Power ON/OFF Switch
Switch Mode Power Supplies (SMPS)
DC to DC Converters
Pulse Transformer Driver
Class D Switching Amplifiers
Power Charge Pumps
*United States Patent 6,917,227
Ordering Information
Part Number
IXDF504PI
IXDF504SIA
IXDF504SIAT/R
IXDF504D1
IXDF504D1T/R
IXDI504PI
IXDI504SIA
IXDI504SIAT/R
IXDI504D1
IXDI504D1T/R
IXDN504PI
IXDN504SIA
IXDN504SIAT/R
IXDN504D1
IXDN504D1T/R
Description
4A Low Side Gate Driver I.C.
4A Low Side Gate Driver I.C.
4A Low Side Gate Driver I.C.
4A Low Side Gate Driver I.C.
4A Low Side Gate Driver I.C.
4A Low Side Gate Driver I.C.
4A Low Side Gate Driver I.C.
4A Low Side Gate Driver I.C.
4A Low Side Gate Driver I.C.
4A Low Side Gate Driver I.C.
4A Low Side Gate Driver I.C.
4A Low Side Gate Driver I.C.
4A Low Side Gate Driver I.C.
4A Low Side Gate Driver I.C.
4A Low Side Gate Driver I.C.
Package
Type
8-Pin PDIP
8-Pin SOIC
8-Pin SOIC
6-Lead DFN
6-Lead DFN
8-Pin PDIP
8-Pin SOIC
8-Pin SOIC
6-Lead DFN
6-Lead DFN
8-Pin PDIP
8-Pin SOIC
8-Pin SOIC
6-Lead DFN
6-Lead DFN
Packing Style
Tube
Tube
13” Tape and Reel
2” x 2” Waffle Pack
13” Tape and Reel
Tube
Tube
13” Tape and Reel
2” x 2” Waffle Pack
13” Tape and Reel
Tube
Tube
13” Tape and Reel
2” x 2” Waffle Pack
13” Tape and Reel
Pack
Qty
50
94
2500
56
2500
50
94
2500
56
2500
50
94
2500
56
2500
Configuration
Dual Drivers,
one Inverting
and one Non-
Inverting
Dual Inverting
Drivers
Dual Non-
Inverting
Drivers
NOTE:
All parts are lead-free and RoHS Compliant
Copyright © 2007 IXYS CORPORATION All rights reserved
DS99567A(10/07)
First Release
IXDF504 / IXDI504 / IXDN504
Figure 1 - IXDF504 Inverting + Non-Inverting 4A Gate Driver Functional Block Diagram
Vcc
P
IN A
ANTI-CROSS
CONDUCTION
CIRCUIT *
OUT A
N
*
P
IN B
ANTI-CROSS
CONDUCTION
CIRCUIT *
OUT B
N
*
GND
Figure 2 - IXDI504 Dual Inverting 4A Gate Driver Functional Block Diagram
Vcc
P
IN A
ANTI-CROSS
CONDUCTION
CIRCUIT *
OUT A
N
*
P
IN B
ANTI-CROSS
CONDUCTION
CIRCUIT *
OUT B
N
*
GND
Figure 3 - IXDN504 Dual 4A Non-Inverting Gate Driver Functional Block Diagram
Vcc
P
IN A
ANTI-CROSS
CONDUCTION
CIRCUIT *
OUT A
N
*
P
IN B
ANTI-CROSS
CONDUCTION
CIRCUIT *
OUT B
N
*
GND
*
United States Patent 6,917,227
Copyright © 2007 IXYS CORPORATION All rights reserved
2
IXDF504 / IXDI504 / IXDN504
Absolute Maximum Ratings
(1)
Parameter
Supply Voltage
All Other Pins (Unless specified
otherwise)
Junction Temperature
Storage Temperature
Lead Temperature (10 Sec)
Value
35 V
-0.3 V to V
CC
+ 0.3V
150
°
C
-65
°
C to 150
°
C
300
°
C
Operating Ratings
(2)
Parameter
Value
Operating Supply Voltage
4.5V to 30V
Operating Temperature Range
-55
°
C to 125
°
C
Package Thermal Resistance
*
θ
J-A
(typ) 125
°
C/W
8-PinPDIP
(PI)
8-Pin SOIC
(SIA)
θ
J-A
(typ) 200
°
C/W
6-Lead DFN
(D1)
θ
J-A
(typ) 125-200
°
C/W
θ
J-C
(max) 2.1
°
C/W
6-Lead DFN
(D1)
6-Lead DFN
(D1)
θ
J-S
(typ)
6.4 °
C/W
Electrical Characteristics @ T
A
= 25
o
C
(3)
Unless otherwise noted, 4.5V
≤
V
CC
≤
30V .
All voltage measurements with respect to GND. IXD_504 configured as described in
Test Conditions.
All specifications are for one channel.
(4)
Symbol
V
IH
V
IL
V
IN
I
IN
V
OH
V
OL
R
OH
R
OL
I
PEAK
I
DC
t
R
t
F
t
ONDLY
t
OFFDLY
V
CC
I
CC
Parameter
High input voltage
Low input voltage
Input voltage range
Input current
High output voltage
Low output voltage
High state output resistance
Low state output resistance
Peak output current
Continuous output current
Rise time
Fall time
On-time propagation delay
Off-time propagation delay
Power supply voltage
Power supply current
Test Conditions
4.5V
≤
V
IN
≤
18V
4.5V
≤
V
IN
≤
18V
Min
3
Typ
Max
Units
V
0.8
-5
V
CC
+ 0.3
10
0.025
-10
V
CC
- 0.025
V
V
µA
V
V
Ω
Ω
A
A
ns
ns
ns
ns
V
µA
mA
mA
0V
≤
V
IN
≤
V
CC
V
CC
= 18V
I
OUT
= 10mA
V
CC
= 18V
I
OUT
= 10mA
V
CC
= 15V
Limited by package
dissipation
C
LOAD
=1000pF
V
CC
=18V
C
LOAD
=1000pF
V
CC
=18V
C
LOAD
=1000pF
V
CC
=18V
C
LOAD
=1000pF
V
CC
=18V
4.5
V
CC
= 18V, V
IN
= 0V
V
IN
= 3.5V
V
IN
= V
CC
1.5
1.2
4
2.5
2
1
9
8
19
18
18
0.25
16
14
40
35
30
10
3
10
IXYS reserves the right to change limits, test conditions, and dimensions.
3
IXDF504 / IXDI504 / IXDN504
Electrical Characteristics @ temperatures over -55
o
C to 125
o
C
(3)
Unless otherwise noted, 4.5V
≤
V
CC
≤
30V , Tj < 150
o
C
All voltage measurements with respect to GND. IXD_504 configured as described in
Test Conditions.
All specifications are for one channel.
Symbol
V
IH
V
IL
V
IN
I
IN
V
OH
V
OL
R
OH
R
OL
I
DC
t
R
t
F
t
ONDLY
t
OFFDLY
V
CC
I
CC
Parameter
High input voltage
Low input voltage
Input voltage range
Input current
High output voltage
Low output voltage
High state output
resistance
Low state output
resistance
Continuous output current
Rise time
Fall time
Test Conditions
4.5V
≤
V
CC
≤
18V
4.5V
≤
V
CC
≤
18V
Min
3
Typ
Max
0.8
Units
V
V
V
µA
V
V
Ω
Ω
A
ns
ns
ns
ns
V
µA
mA
mA
-5
0V
≤
V
IN
≤
V
CC
-10
V
CC
- 0.025
V
CC
+ 0.3
10
0.025
V
CC
= 18V, I
OUT
= 10mA
V
CC
= 18V, I
OUT
= 10mA
3
2.5
1
20
15
60
50
4.5
18
30
150
3
150
C
LOAD
=1000pF V
CC
=18V
C
LOAD
=1000pF V
CC
=18V
On-time propagation delay C
LOAD
=1000pF V
CC
=18V
Off-time propagation delay C
LOAD
=1000pF V
CC
=18V
Power supply voltage
Power supply current
V
CC
= 18V, V
IN
= 0V
V
IN
= 3.5V
V
IN
= V
CC
Notes:
1. Operating the device beyond the parameters listed as “Absolute Maximum Ratings” may cause permanent
damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.
2. The device is not intended to be operated outside of the Operating Ratings.
3. Electrical Characteristics provided are associated with the stated Test Conditions.
4. Typical values are presented in order to communicate how the device is expected to perform, but not necessarily
to highlight any specific performance limits within which the device is guaranteed to function.
1) The
θ
J-A
(typ) is defined as junction to ambient. The
θ
J-A
of the standard single die 8-Lead PDIP and 8-Lead SOIC are dominated by the
resistance of the package, and the IXD_5XX are typical. The values for these packages are natural convection values with vertical boards
and the values would be lower with forced convection. For the 6-Lead DFN package, the
θ
J-A
value supposes the DFN package is soldered
on a PCB. The
θ
J-A
(typ) is 200
°
C/W with no special provisions on the PCB, but because the center pad provides a low thermal resistance
to the die, it is easy to reduce the
θ
J-A
by adding connected copper pads or traces on the PCB. These can reduce the
θ
J-A
(typ) to 125
°
C/W
easily, and potentially even lower. The
θ
J-A
for DFN on PCB without heatsink or thermal management will vary significantly with size,
construction, layout, materials, etc. This typical range tells the user what he is likely to get if he does no thermal management.
2)
θ
J-C
(max) is defined as juction to case, where case is the large pad on the back of the DFN package. The
θ
J-C
values are generally not
published for the PDIP and SOIC packages. The
θ
J-C
for the DFN packages are important to show the low thermal resistance from junction to
the die attach pad on the back of the DFN, -- and a guardband has been added to be safe.
3) The
θ
J-S
(typ) is defined as junction to heatsink, where the DFN package is soldered to a thermal substrate that is mounted on a heatsink.
The value must be typical because there are a variety of thermal substrates. This value was calculated based on easily available IMS in the
U.S. or Europe, and not a premium Japanese IMS. A 4 mil dialectric with a thermal conductivity of 2.2W/mC was assumed. The result was
given as typical, and indicates what a user would expect on a typical IMS substrate, and shows the potential low thermal resistance for the
DFN package.
*
The following notes are meant to define the conditions for the
θ
J-A
,
θ
J-C
and
θ
J-S
values:
Copyright © 2007 IXYS CORPORATION All rights reserved
4
IXDF504 / IXDI504 / IXDN504
Pin Description
SYMBOL
IN A
GND
IN B
OUT B
VCC
OUT A
FUNCTION
A Channel Input
Ground
B Channel Input
B Channel Output
Supply Voltage
A Channel Output
DESCRIPTION
A channel input signal-TTL or CMOS compatible.
The system ground pin. Internally connected to all circuitry, this pin provides
ground reference for the entire device. This pin should be connected to a
low noise analog ground plane for optimum performance.
B channel input signal-TTL or CMOS compatible.
B channel driver output. For application purposes, this pin is connected via a
resistor to the gate of a MOSFET/IGBT.
Positive power-supply voltage input. This pin provides power to the entire
device. The range for this voltage is from 4.5V to 30V.
A channel criver output. For application purposes, this pin is connected via a
resistor to the gate of a MOSFET/IGBT.
CAUTION: Follow proper ESD procedures when handling and assembling this component.
Pin Configurations
IXDF504
1
2
3
4
IXDI504
8
7
1
2
3
4
IXDN504
8
7
1
2
3
4
NC
IN A
GND
INB
NC
O UT A
NC
IN A
GND
INB
NC
O UT A
NC
IN A
GND
INB
NC
O UT A
8
7
V
S
6
O UT B 5
V
S
6
O UT B 5
V
S
6
O UT B 5
8 Lead PDIP (PI)
8 Pin SOIC (SI)
(SIA)
IXDF402
8 Lead PDIP (PI)
8 Pin SOIC (SI)
(SIA)
IXDI402
8 Lead PDIP (PI)
(SIA)
8 Pin SOIC (SI)
IXDN402
6 Lead DFN (D1)
(Bottom View)
6 Lead DFN (D1)
(Bottom View)
6 Lead DFN (D1)
(Bottom View)
6 OUT A IN A 1
5 Vcc
4 OUT B
GND 2
IN B 3
6 OUT A IN A 1
5 Vcc
4 OUT B
GND 2
IN B 3
6 OUT A
5
Vcc
IN A 1
GND 2
IN B 3
4 OUT B
NOTE:
Solder tabs on bottoms of DFN packages are grounded
Figure 4 - Characteristics Test Diagram
Vcc
IXD_504
1
NC
2
In A
3
Gnd
4
In B
NC 8
7
Out A
6
Vcc
5
Out B
Agilent 1147A
Current Probe
C
LOAD
Agilent 1147A
Current Probe
C
LOAD
10uF
0.01uF
IXYS reserves the right to change limits, test conditions, and dimensions.
5
模拟与混合信号
