Cortina Systems
®
IXF1010 10-Port 100/
1000 Mbps Ethernet Media Access
Controller
Datasheet
The Cortina Systems
®
IXF1010 10-Port 100/1000 Mbps Ethernet Media Access Controller
(IXF1010 MAC) is a 10-port Ethernet Media Access Controller (MAC) that supports IEEE 802.3 100 and
1000 Mbps applications. The device supports a System Packet Interface Level 4 Phase 2 (SPI4-2)
system interface to the network processor or ASIC.
The IXF1010 MAC implements the Reduced Gigabit Media Independent Interface (RGMII), as defined in
Version 1.2a of the Hewlett-Packard* specification for PHY connectivity. The RGMII reduces the
interface ball count from GMII to allow for higher port densities.
Applications
In general, the IXF1010 MAC is appropriate for high-end switching applications where MAC and PHY
functions are not integrated into the system ASIC.
High-End Ethernet Switches
Multi-Service Ethernet Switches
High-End Ethernet LAN/WAN Routers
Product Features
RGMII interface with optical module
connections/MDIO for Ethernet physical
connectivity
System Packet Interface Level 4 Phase 2
(SPI4-2)
Capable of data transfers from 10.24 Gbps up
to 12.8 Gbps
Supports dynamic phase alignment
Integrated termination
Ten independent 100/1000 Mbps full-duplex
Ethernet MAC ports
32-bit CPU interface
Operating Temperature Range:
— Min: 0 °C Max: +70 °C
RMON statistics
JTAG boundary scan
Compliant with IEEE 802.3x Standard for flow
control
Jumbo frame support for 9.6 KB packets
.18
μ
CMOS process technology
Internal 17.0 KB receive FIFO and 4.5 KB
transmit FIFO per port
Independent enable/disable of any port
Detection of short or overly large packets
Counters for dropped and errored packets
CRC calculation and error detection
Programmable options:
— Filter packets with errors
— Filter, broadcast, multicast, and unicast
address packets
— Automatically pad transmitted packets
less than the minimum frame size
552-Ceramic BGA (RoHS-compliant)
1.8 V and 2.5 V operation
Power consumption: 480 mW per-port typical
IXF1010 MAC
Datasheet
249839, Revision 10.0
5 July 2007
Legal Disclaimers
This document contains information proprietary to Cortina Systems, Inc. (Cortina). Any use or disclosure, in whole or in part, of this
information to any unauthorized party, for any purposes other than that for which it is provided is expressly prohibited except as
authorized by Cortina in writing. Cortina reserves its rights to pursue both civil and criminal penalties for copying or disclosure of
this material without authorization.
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH CORTINA SYSTEMS
®
PRODUCTS.
NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS
GRANTED BY THIS DOCUMENT.
EXCEPT AS PROVIDED IN CORTINA’S TERMS AND CONDITIONS OF SALE OF SUCH PRODUCTS, CORTINA ASSUMES
NO LIABILITY WHATSOEVER, AND CORTINA DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO THE
SALE AND/OR USE OF CORTINA PRODUCTS, INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A
PARTICULAR PURPOSE, MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT.
Cortina products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear
facility applications.
Cortina Systems
®
and the Cortina Systems logo are the trademarks or registered trademarks of Cortina Systems, Inc. and its
subsidiaries in the U.S. and other countries. Other names and brands may be claimed as the property of others.
Copyright © 2007 Cortina Systems, Inc. All rights reserved.
Cortina Systems
®
IXF1010 10-Port 100/1000 Mbps Ethernet Media Access Controller
Page 2
IXF1010 MAC
Datasheet
249839, Revision 10.0
5 July 2007
Contents
Contents
1.0
Introduction.................................................................................................................................. 13
1.1
1.2
2.0
3.0
4.0
What You Will Find in This Document ................................................................................ 13
Related Documents ............................................................................................................ 13
General Description .................................................................................................................... 15
Ball Assignments and Ball List Tables...................................................................................... 17
Ball Assignments and Signal Descriptions .............................................................................. 18
4.1
4.2
4.3
Naming Conventions ..........................................................................................................18
4.1.1 Signal Name Conventions ..................................................................................... 18
4.1.2 Register Address Conventions .............................................................................. 18
Interface Signal Groups ...................................................................................................... 18
Ball List Tables ................................................................................................................... 29
4.3.1 Balls Listed in Alphanumeric Order by Signal Name ............................................. 29
4.3.2 Balls Listed in Alphanumeric Order by Ball Location ............................................. 34
Media Access Controller .....................................................................................................40
5.1.1 General Description ............................................................................................... 40
5.1.2 MAC Functions ...................................................................................................... 40
5.1.3 Flow Control...........................................................................................................43
5.1.4 Auto-Negotiation .................................................................................................... 47
5.1.5 Jumbo Packet Support .......................................................................................... 48
5.1.6 RMON Statistics Support ....................................................................................... 49
System Packet Interface Level 4 Phase 2 .......................................................................... 51
5.2.1 Data Path ............................................................................................................... 53
5.2.2 Start-Up Parameters ..............................................................................................58
5.2.3 Dynamic Phase Alignment Training Sequence (Data Path De-skew) ................... 60
5.2.4 FIFO Status Channel ............................................................................................. 61
5.2.5 DC Parameters ...................................................................................................... 65
Reduced Gigabit Media Independent Interface (RGMII) ....................................................65
5.3.1 Purpose ................................................................................................................. 65
5.3.2 Configuring the IXF1010 MAC for RGMII Operation.............................................. 65
5.3.3 MAC/PHY Interface, Signaling, and Operation ...................................................... 65
5.3.4 1000 Mbps Operation ............................................................................................ 66
5.3.5 100 Mbps Operation ..............................................................................................68
5.3.6 Timing Specifics..................................................................................................... 68
5.3.7 Electrical Characteristics........................................................................................ 69
MDIO Control and Interface ................................................................................................ 69
5.4.1 MDIO Interface ...................................................................................................... 69
5.4.2 General Description ............................................................................................... 69
5.4.3 Single MDI Command Operation ........................................................................... 69
5.4.4 Clear When Done .................................................................................................. 69
5.4.5 MDC Generation .................................................................................................... 70
5.4.6 MDIO Management Frames .................................................................................. 71
5.4.7 MDI State Machine ................................................................................................ 71
5.4.8 Autoscan Operation ............................................................................................... 72
5.4.9 MDIO Register Descriptions .................................................................................. 73
5.0
Functional Description................................................................................................................ 40
5.1
5.2
5.3
5.4
Cortina Systems
®
IXF1010 10-Port 100/1000 Mbps Ethernet Media Access Controller
Page 3
IXF1010 MAC
Datasheet
249839, Revision 10.0
5 July 2007
Contents
5.5
5.6
5.7
5.8
LED Interface...................................................................................................................... 73
5.5.1 Introduction ............................................................................................................ 73
5.5.2 Modes of Operation ............................................................................................... 73
5.5.3 LED Interface Signal Description ........................................................................... 74
5.5.4 Mode 0: Detailed Operation ................................................................................... 74
5.5.5 Mode 1: Detailed Operation ................................................................................... 75
5.5.6 Power-On, Reset, and Initialization ....................................................................... 76
5.5.7 LED Data Decodes ................................................................................................ 77
CPU Interface ..................................................................................................................... 78
5.6.1 General Description ............................................................................................... 78
5.6.2 Functional Description ........................................................................................... 79
5.6.3 Endian....................................................................................................................82
JTAG (Boundary Scan)....................................................................................................... 82
5.7.1 TAP Interface (JTAG) ............................................................................................ 82
5.7.2 TAP State Machine ................................................................................................ 83
5.7.3 Instruction Register and Supported Instructions ....................................................83
5.7.4 ID Register ............................................................................................................. 83
5.7.5 Boundary Scan Register ........................................................................................ 83
5.7.6 Bypass Register..................................................................................................... 83
Clocks ................................................................................................................................. 84
5.8.1 System Interface Reference Clocks....................................................................... 84
5.8.2 SPI4-2 Receive and Transmit Data Path Clocks ................................................... 84
5.8.3 RGMII Clocks......................................................................................................... 85
5.8.4 MDC Clock............................................................................................................. 85
5.8.5 JTAG Clock............................................................................................................ 85
5.8.6 LED Clock .............................................................................................................. 85
Power Supply Sequencing.................................................................................................. 86
6.1.1 Power-Up Sequence..............................................................................................86
6.1.2 Power-Down Sequence ......................................................................................... 86
Analog Power Filtering........................................................................................................ 87
TX FIFO and RX FIFO Operation ....................................................................................... 87
6.3.1 TX FIFO ................................................................................................................. 88
6.3.2 RX FIFO................................................................................................................. 90
Reset and Initialization........................................................................................................ 91
6.4.1 SPI4-2 Initialization ................................................................................................ 91
IXF1010 MAC Unused Ports ..............................................................................................92
DC Specifications ............................................................................................................... 94
Undershoot/Overshoot Specifications ................................................................................ 95
RGMII Timing Specifications ..............................................................................................96
MDIO Timing Specifications ............................................................................................... 98
CPU Timing Specification .................................................................................................100
JTAG Timing Specification ...............................................................................................101
Transmit Pause Control Timing Specifications .................................................................102
System Timing Specifications ...........................................................................................103
LED Timing Specifications................................................................................................103
SPI4-2 Timing Specifications ............................................................................................105
6.0
Applications ................................................................................................................................. 86
6.1
6.2
6.3
6.4
6.5
7.0
Electrical Specifications ............................................................................................................. 93
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
Cortina Systems
®
IXF1010 10-Port 100/1000 Mbps Ethernet Media Access Controller
Page 4
IXF1010 MAC
Datasheet
249839, Revision 10.0
5 July 2007
Contents
8.0
Register Definitions...................................................................................................................107
8.1
8.2
8.3
8.4
8.5
Introduction .......................................................................................................................107
Document Structure ..........................................................................................................107
Graphical Representation .................................................................................................107
Per Port Registers ............................................................................................................108
Memory Map .....................................................................................................................109
8.5.1 MAC Control Registers ........................................................................................116
8.5.2 MAC RX Statistics Register Overview .................................................................123
8.5.3 MAC TX Statistics Register Overview..................................................................126
8.5.4 PHY Autoscan Registers .....................................................................................129
8.5.5 Global Status and Configuration Register Overview............................................135
8.5.6 Global RX Block Register Overview ....................................................................141
8.5.7 TX Block Register Overview ................................................................................150
8.5.8 MDIO Block Register Overview ...........................................................................160
8.5.9 SPI4-2 Block Register Overview..........................................................................162
Features............................................................................................................................165
IXF1010 MAC Package Specifics .....................................................................................165
9.2.1 Markings ..............................................................................................................165
9.0
Mechanical Specifications ........................................................................................................165
9.1
9.2
10.0 Product Ordering Information ..................................................................................................169
Cortina Systems
®
IXF1010 10-Port 100/1000 Mbps Ethernet Media Access Controller
Page 5
